fix: port Pipeline7 optimizations into preload-compatible Pipeline9 - #2185
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/benchmark --same-machine --pipeline 9 --dataset 18 |
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/benchmark --same-machine --dataset 18 |
Same Machine Benchmark ResultsBoth revisions ran sequentially in one Blacksmith job on Dataset:
Outcome changes: 12 improved, 0 regressed. DRC issues are totaled across solved samples. Timing percentiles include solved and timed-out samples; negative timing deltas are faster. Changed outcomes (12)
Workflow: View run |
Same Machine Benchmark ResultsBoth revisions ran sequentially in one Blacksmith job on Dataset:
Outcome changes: 0 improved, 0 regressed. DRC issues are totaled across solved samples. Timing percentiles include solved and timed-out samples; negative timing deltas are faster. Workflow: View run |
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/benchmark --same-machine --pipeline 9 --dataset 18 |
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/benchmark --same-machine --dataset 18 |
Same Machine Benchmark ResultsBoth revisions ran sequentially in one Blacksmith job on Dataset:
Outcome changes: 3 improved, 0 regressed. DRC issues are totaled across solved samples. Timing percentiles include solved and timed-out samples; negative timing deltas are faster. Changed outcomes (3)
Workflow: View run |
Same Machine Benchmark ResultsBoth revisions ran sequentially in one Blacksmith job on Dataset:
Outcome changes: 1 improved, 0 regressed. DRC issues are totaled across solved samples. Timing percentiles include solved and timed-out samples; negative timing deltas are faster. Changed outcomes (1)
Workflow: View run |
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/benchmark --same-machine --pipeline 9 --dataset 23 |
Same Machine Benchmark ResultsBoth revisions ran sequentially in one Blacksmith job on Dataset:
Outcome changes: 4 improved, 1 regressed. DRC issues are totaled across solved samples. Timing percentiles include solved and timed-out samples; negative timing deltas are faster. Changed outcomes (5)
Workflow: View run |
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/benchmark --same-machine --pipeline 9 --dataset 18 |
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/benchmark --same-machine --dataset 18 |
Same Machine Benchmark ResultsBoth revisions ran sequentially in one Blacksmith job on Dataset:
Outcome changes: 4 improved, 1 regressed. DRC issues are totaled across solved samples. Timing percentiles include solved and timed-out samples; negative timing deltas are faster. Changed outcomes (5)
Workflow: View run |
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/benchmark --same-machine --pipeline 9 --dataset 23 |
Same Machine Benchmark ResultsBoth revisions ran sequentially in one Blacksmith job on Dataset:
Outcome changes: 4 improved, 3 regressed. DRC issues are totaled across solved samples. Timing percentiles include solved and timed-out samples; negative timing deltas are faster. Changed outcomes (7)
Workflow: View run |
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Final cross-solver parity check on one warmed Blacksmith 4-vCPU Testbox (serial Pipeline7 then Pipeline9, SRJ18, concurrency 4): both 81.3% completion / 50.0% relaxed DRC / 1 timeout. Pipeline9 P50 91.0s vs 103.9s (-12.5%) and P95 332.5s vs 343.8s (-3.3%); average vias 206.38 vs 209.46. Full percentile table is now in the PR body. Testbox workflow: https://github.com/tscircuit/tscircuit-autorouter/actions/runs/32476897633 |
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/benchmark --same-machine --pipeline 7 --dataset 18 |
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/benchmark --same-machine --pipeline 9 --dataset 18 |
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/benchmark --pipeline 9 |
Same Machine Benchmark ResultsBoth revisions ran sequentially in one Blacksmith job on Dataset:
Outcome changes: 0 improved, 0 regressed. DRC issues are totaled across solved samples. Timing percentiles include solved and timed-out samples; negative timing deltas are faster. Workflow: View run |
Same Machine Benchmark ResultsBoth revisions ran sequentially in one Blacksmith job on Dataset:
Outcome changes: 12 improved, 0 regressed. DRC issues are totaled across solved samples. Timing percentiles include solved and timed-out samples; negative timing deltas are faster. Changed outcomes (12)
Workflow: View run |
Default Benchmark ResultsMain vs PRDataset: dataset01 · Scenarios: 85 · Effort: 1x effort
DRC issues are totaled across solved samples. Timing percentiles include solved and timed-out samples; negative timing changes are faster. Previous main run details
PR run details
Workflow: View run |
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Goal
Make Pipeline9 match Pipeline7's completion, relaxed-DRC quality, and speed while keeping one preload-compatible pipeline for every input. A board with one preloaded trace runs the same stage list and solver configuration as a board with none; this PR does not delegate trace-free boards to Pipeline7 or disable preload features.
What changed
through_obstacleprimitives.Preload invariant
There is no preload-count branch that changes Pipeline9's stage list or swaps in a separate Pipeline7 pipeline. Preloaded routes remain movable when they are the only blocker, but ordinary routes are preferred for rerip first. Immutable preloads are carried into every fallback as indexed, layer-aware copper obstacles and final candidate geometry is checked before acceptance.
Regional repair is entered from the identities in the remaining DRC errors, not from the number of preloaded traces. Once a real preload-owned conflict activates that bounded joint pass, it can also clear supported ordinary errors in the same region.
Dependency PRs
The package pins use the exact tested heads of those PRs.
Final benchmark evidence
Serial Pipeline7 then Pipeline9 runs on the same warmed Blacksmith 4-vCPU Testbox, SRJ18, concurrency 4. The measured head is byte-for-byte identical to the current head for Pipeline7 and Pipeline9; the two later commits only restore legal-layer routing in Pipeline4 and increase the CI job timeout:
Pipeline9 matches Pipeline7's completion, relaxed-DRC pass rate, and timeout count. It is faster at P50, P60, and P95 and slower at P70, P80, and P90, with the largest gap +15.9% at P70. Both pipelines share the same remaining timeout (sample 6) and tiny-hypergraph failures (samples 14/15).
Same-machine main-vs-PR workflow results:
Validation
bun run buildbunx tsc --noEmit