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Run tiny-hypergraph region cost optimizer - #2152

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Run tiny-hypergraph region cost optimizer#2152
seveibar wants to merge 15 commits into
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agent/integrate-tiny-hypergraph-166-region-cost

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Summary

  • pin tiny-hypergraph to Add post-solve region cost optimizer tiny-hypergraph#166 at 85733078
  • configure routing-complexity region costs and preserve preloaded routes as fixed optimizer inputs
  • consume the completed optimizeRegionCosts stage for downstream routing and visualization
  • add integration coverage proving the optimizer runs and supplies the solved graph

Validation

  • bun test tests/tinyhypergraph-post-solve-region-optimizer.test.ts tests/tinyhypergraph-terminal-port-ids.test.ts tests/tinyhypergraph-pipeline-error-propagation.test.ts tests/solvers/tinyhypergraph-candidate-portfolio.test.ts tests/features/partial-rip-preloaded-trace-occupancy.test.ts tests/features/tinyhypergraph-port-bridge-repro.test.ts tests/pipeline-immutability/autorouting-pipeline4-tiny-hypergraph.test.ts tests/features/pipeline7-full-pipeline-svg-frames.test.ts tests/e2e3-multisection.test.ts --timeout 9999999 — 12 passed
  • bunx tsc --noEmit
  • bun run build
  • git diff --check

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/benchmark --same-machine --dataset 18

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vercel Bot commented Aug 18, 2026

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The latest updates on your projects. Learn more about Vercel for GitHub.

Project Deployment Actions Updated (UTC)
capacity-node-autorouter Ready Ready Preview Aug 26, 2026 7:30pm

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Benchmark This PR

Run benchmarks by commenting on this PR:

/benchmark [benchmark.sh args...]
/benchmark-long [benchmark.sh args...]
/benchmark-all
/benchmark --same-machine
/benchmark-all --same-machine

Comment /benchmark to run the default dataset, or append any arguments accepted by ./benchmark.sh.
Comment /benchmark-long for an 8-vCPU run that defaults to 8 workers and has an eight-hour timeout.
Comment exactly /benchmark-all to start separate workflow runs and result comments for the default dataset plus srj18, srj19, srj20, srj21, and srj23.
Append --same-machine to /benchmark or /benchmark-all to compare current main and the PR head sequentially on the same 8-vCPU Blacksmith runner.

Everything after /benchmark or /benchmark-long is safely forwarded to ./benchmark.sh, except --profile-solvers, which enables profile comparison tables, and --same-machine, which enables the paired runner.
Examples: /benchmark --dataset 18 --sample-timeout 2000s, /benchmark --pipeline 10 --dataset 29, /benchmark --pipeline 10 --dataset 29 --sample 1, /benchmark --pipeline 7 --limit 20, /benchmark all 20 --concurrency 8, /benchmark --same-machine, /benchmark-all --same-machine, and /benchmark-long --dataset 18.

Use /update-snapshots (or /us) to run BUN_UPDATE_SNAPSHOTS=1 bun test --timeout 120_000 on the PR branch and auto-commit snapshot updates.
Use /usf to read recent failed test files, update and verify their exact CI test shards, and auto-commit only their snapshots. It uses the configured fast benchmark runner by default; use /usf --ubuntu-latest for GitHub-hosted x64 CI parity.

Any PR whose title contains [BENCHMARK TEST] will automatically run one default-dataset benchmark on PR updates; it does not post a PR result comment.

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Same Machine Benchmark Results

Both revisions ran sequentially in one Blacksmith job on blacksmith-01m0b76sjtxe44ra307xcdjpbh-8vcpu.

Dataset: srj18 · Scenarios: 16
Main: 2601b9e · PR: a88ac3a

Solver Metric Main PR Delta
Pipeline7 Completion 75.0% (🕒12.5%) 75.0% (🕒18.8%) 0.0 pp
Pipeline7 Relaxed DRC pass 43.8% (🕒12.5%) 50.0% (🕒18.8%) +6.2 pp
Pipeline7 Timeouts 2 3 +1
Pipeline7 P50 time 124.3s 156.2s +25.7%
Pipeline7 P60 time 139.4s 239.9s +72.1%
Pipeline7 P70 time 188.4s 300.6s +59.6%
Pipeline7 P80 time 252.8s 337.8s +33.6%
Pipeline7 P90 time 339.6s 360.0s +6.0%
Pipeline7 P95 time 360.0s 360.0s 0.0%
Pipeline7 Average vias 179.92 199.08 +10.7%

Outcome changes: 1 improved, 1 regressed. Timing percentiles include solved and timed-out samples; negative timing deltas are faster.

Changed outcomes (2)
Solver Sample Main PR Main time PR time Delta
Pipeline7 2 Timeout DRC passed 360.0s 298.6s Improved
Pipeline7 8 Solved (DRC failed) Failed 184.1s 223.2s Regressed

Workflow: View run
Artifact: Download raw reports

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/benchmark --same-machine --dataset 18

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Same Machine Benchmark Results

Both revisions ran sequentially in one Blacksmith job on blacksmith-01m0b9n92144hxhwcmjp3qg185-8vcpu.

Dataset: srj18 · Scenarios: 16
Main: 78dbe5a · PR: 3daaf9a

Solver Metric Main PR Delta
Pipeline7 Completion 75.0% (🕒12.5%) 75.0% (🕒18.8%) 0.0 pp
Pipeline7 Relaxed DRC pass 43.8% (🕒12.5%) 50.0% (🕒18.8%) +6.2 pp
Pipeline7 Timeouts 2 3 +1
Pipeline7 P50 time 130.7s 146.9s +12.4%
Pipeline7 P60 time 145.4s 225.5s +55.1%
Pipeline7 P70 time 196.3s 281.4s +43.4%
Pipeline7 P80 time 268.7s 326.6s +21.5%
Pipeline7 P90 time 339.9s 360.0s +5.9%
Pipeline7 P95 time 360.0s 360.0s 0.0%
Pipeline7 Average vias 179.92 199.08 +10.7%

Outcome changes: 1 improved, 1 regressed. Timing percentiles include solved and timed-out samples; negative timing deltas are faster.

Changed outcomes (2)
Solver Sample Main PR Main time PR time Delta
Pipeline7 2 Timeout DRC passed 360.0s 283.1s Improved
Pipeline7 8 Solved (DRC failed) Failed 190.0s 199.6s Regressed

Workflow: View run
Artifact: Download raw reports

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/benchmark-long --dataset 18 --sample-timeout 7200s

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tscircuitbot commented Aug 18, 2026

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18 Results

Main vs PR

Dataset: srj18 · Scenarios: 16 · Effort: 1x effort

Solver Metric Main PR Change
Pipeline7 Completion 81.3% (🕒6.3%) 93.8% +12.5 pp
Pipeline7 Relaxed DRC pass 43.8% (🕒6.3%) 43.8% 0.0 pp
Pipeline7 Timeouts 1 0 -1
Pipeline7 P50 time 105.2s 174.3s +65.7%
Pipeline7 P60 time 126.0s 256.9s +104.0%
Pipeline7 P70 time 161.7s 327.8s +102.8%
Pipeline7 P80 time 241.9s 369.3s +52.7%
Pipeline7 P90 time 310.6s 519.1s +67.2%
Pipeline7 P95 time 340.3s 619.9s +82.1%
Pipeline7 Average vias 208.38 212.27 +1.9%

Timing percentiles include solved and timed-out samples. Negative timing changes are faster.

Previous main run details
Solver Sample Status Via Time Relaxed DRC Error
Pipeline7 1 Solved 184 28.8s Passed
Pipeline7 2 Solved 550 329.7s Failed
Pipeline7 3 Solved 90 33.6s Passed
Pipeline7 4 Solved 131 104.3s Failed
Pipeline7 5 Solved 146 25.4s Passed
Pipeline7 6 Timeout 360.0s Failed
HighDensitySolverPhase: highDensityRouteSolver
Timed out after 360.0s
Last progress: phase=highDensityRouteSolver, solver=HighDensitySolver, pipelineIterations=2308851, phaseIterations=277805, pipelineProgress=0%, phaseProgress=0%
Pipeline7 7 Solved 231 50.2s Passed
Pipeline7 8 Solved 295 154.6s Failed
Pipeline7 9 Solved 124 76.3s Failed
Pipeline7 10 Solved 171 130.9s Passed
Pipeline7 11 Solved 179 106.0s Passed
Pipeline7 12 Solved 292 265.9s Passed
Pipeline7 13 Solved 216 225.8s Failed
Pipeline7 14 Failed 121.8s Failed
TinyHypergraphPortPointPathingSolverPhase: portPointPathingSolver
SelectiveReripTinyHyperGraphSolverWithStableInitialAssignments ran out of iterations
Pipeline7 15 Failed 94.0s Failed
TinyHypergraphPortPointPathingSolverPhase: portPointPathingSolver
SelectiveReripTinyHyperGraphSolverWithStableInitialAssignments ran out of iterations
Pipeline7 16 Solved 100 62.0s Failed
PR run details
Solver Sample Status Via Time Relaxed DRC Error Delta
Pipeline7 1 Solved 178 (-6, better) 48.4s Passed
Pipeline7 2 Solved 437 335.7s Failed
Pipeline7 3 Solved 89 (+2, worse) 43.1s Passed
Pipeline7 4 Solved 161 174.3s Failed
Pipeline7 5 Solved 146 (+43, worse) 37.9s Passed
Pipeline7 6 Solved 301 830.5s Failed Improved
Pipeline7 7 Solved 216 (-15, better) 99.7s Passed
Pipeline7 8 Failed 215.4s Failed
MultipleHighDensityRouteStitchSolver3Phase: highDensityStitchSolver
AutoroutingPipelineSolver7_MultiGraph error: Error: SingleHighDensityRouteStitchSolver3 found unknown PCB terminal "pcb_port_71" on "source_trace_9__source_net_9_mst29"
Regressed
Pipeline7 9 Solved 121 75.1s Failed
Pipeline7 10 Solved 164 (+10, worse) 209.9s Passed
Pipeline7 11 Solved 179 (+3, worse) 131.8s Passed
Pipeline7 12 Solved 292 (=best) 327.4s Passed
Pipeline7 13 Solved 205 327.9s Failed
Pipeline7 14 Solved 296 503.4s Failed Improved
Pipeline7 15 Solved 302 529.6s Failed Improved
Pipeline7 16 Solved 97 77.8s Failed

Workflow: View run
Artifact: https://github.com/tscircuit/tscircuit-autorouter/actions/runs/32186809727

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/benchmark-long --dataset 18 --sample-timeout 7200s

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tscircuitbot commented Aug 19, 2026

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18 Results

Main vs PR

Dataset: srj18 · Scenarios: 16 · Effort: 1x effort

Solver Metric Main PR Change
Pipeline7 Completion 81.3% (🕒6.3%) 93.8% +12.5 pp
Pipeline7 Relaxed DRC pass 43.8% (🕒6.3%) 50.0% +6.2 pp
Pipeline7 Timeouts 1 0 -1
Pipeline7 P50 time 106.4s 185.0s +73.8%
Pipeline7 P60 time 121.3s 279.4s +130.2%
Pipeline7 P70 time 171.5s 357.4s +108.3%
Pipeline7 P80 time 234.5s 399.4s +70.3%
Pipeline7 P90 time 310.5s 568.5s +83.1%
Pipeline7 P95 time 345.1s 674.2s +95.4%
Pipeline7 Average vias 208.38 218.00 +4.6%

Timing percentiles include solved and timed-out samples. Negative timing changes are faster.

Previous main run details
Solver Sample Status Via Time Relaxed DRC Error
Pipeline7 1 Solved 184 30.5s Passed
Pipeline7 2 Solved 550 337.0s Failed
Pipeline7 3 Solved 90 36.0s Passed
Pipeline7 4 Solved 131 104.7s Failed
Pipeline7 5 Solved 146 27.0s Passed
Pipeline7 6 Timeout 360.0s Failed
HighDensitySolverPhase: highDensityRouteSolver
Timed out after 360.0s
Last progress: phase=highDensityRouteSolver, solver=HighDensitySolver, pipelineIterations=2309704, phaseIterations=278658, pipelineProgress=0%, phaseProgress=0%
Pipeline7 7 Solved 231 45.6s Passed
Pipeline7 8 Solved 295 165.6s Failed
Pipeline7 9 Solved 124 68.5s Failed
Pipeline7 10 Solved 171 124.6s Passed
Pipeline7 11 Solved 179 108.2s Passed
Pipeline7 12 Solved 292 248.7s Passed
Pipeline7 13 Solved 216 225.1s Failed
Pipeline7 14 Failed 127.4s Failed
TinyHypergraphPortPointPathingSolverPhase: portPointPathingSolver
SelectiveReripTinyHyperGraphSolverWithStableInitialAssignments ran out of iterations
Pipeline7 15 Failed 93.9s Failed
TinyHypergraphPortPointPathingSolverPhase: portPointPathingSolver
SelectiveReripTinyHyperGraphSolverWithStableInitialAssignments ran out of iterations
Pipeline7 16 Solved 100 61.9s Failed
PR run details
Solver Sample Status Via Time Relaxed DRC Error Delta
Pipeline7 1 Solved 184 (=best) 59.2s Passed
Pipeline7 2 Solved 503 359.4s Passed Improved
Pipeline7 3 Solved 89 (-1, better) 53.5s Passed
Pipeline7 4 Solved 161 185.0s Failed
Pipeline7 5 Solved 146 (+43, worse) 49.5s Passed
Pipeline7 6 Solved 301 906.8s Failed Improved
Pipeline7 7 Solved 231 (=best) 112.2s Passed
Pipeline7 8 Failed 231.2s Failed
MultipleHighDensityRouteStitchSolver3Phase: highDensityStitchSolver
AutoroutingPipelineSolver7_MultiGraph error: Error: SingleHighDensityRouteStitchSolver3 found unknown PCB terminal "pcb_port_71" on "source_trace_9__source_net_9_mst29"
Regressed
Pipeline7 9 Solved 121 89.0s Failed
Pipeline7 10 Solved 164 (-7, better) 231.7s Passed
Pipeline7 11 Solved 179 (=best) 156.1s Passed
Pipeline7 12 Solved 291 (-1, better) 350.9s Passed
Pipeline7 13 Solved 205 359.0s Failed
Pipeline7 14 Solved 296 559.6s Failed Improved
Pipeline7 15 Solved 302 574.5s Failed Improved
Pipeline7 16 Solved 97 81.5s Failed

Workflow: View run
Artifact: https://github.com/tscircuit/tscircuit-autorouter/actions/runs/32277679151

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/benchmark-long --dataset 18 --sample-timeout 7200s

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18 Results

Main vs PR

Dataset: srj18 · Scenarios: 16 · Effort: 1x effort

Solver Metric Main PR Change
Pipeline7 Completion 81.3% (🕒6.3%) 93.8% +12.5 pp
Pipeline7 Relaxed DRC pass 43.8% (🕒6.3%) 43.8% 0.0 pp
Pipeline7 Timeouts 1 0 -1
Pipeline7 P50 time 106.0s 178.4s +68.3%
Pipeline7 P60 time 120.3s 277.1s +130.4%
Pipeline7 P70 time 174.1s 371.7s +113.5%
Pipeline7 P80 time 237.2s 409.5s +72.6%
Pipeline7 P90 time 309.0s 801.4s +159.4%
Pipeline7 P95 time 343.0s 1012.1s +195.1%
Pipeline7 Average vias 208.38 217.13 +4.2%

Timing percentiles include solved and timed-out samples. Negative timing changes are faster.

Previous main run details
Solver Sample Status Via Time Relaxed DRC Error
Pipeline7 1 Solved 184 29.7s Passed
Pipeline7 2 Solved 550 333.9s Failed
Pipeline7 3 Solved 90 33.7s Passed
Pipeline7 4 Solved 131 103.5s Failed
Pipeline7 5 Solved 146 26.2s Passed
Pipeline7 6 Timeout 360.0s Failed
HighDensitySolverPhase: highDensityRouteSolver
Timed out after 360.0s
Last progress: phase=highDensityRouteSolver, solver=HighDensitySolver, pipelineIterations=2434572, phaseIterations=403526, pipelineProgress=0%, phaseProgress=0%
Pipeline7 7 Solved 231 45.0s Passed
Pipeline7 8 Solved 295 168.1s Failed
Pipeline7 9 Solved 124 66.0s Failed
Pipeline7 10 Solved 171 123.2s Passed
Pipeline7 11 Solved 179 108.6s Passed
Pipeline7 12 Solved 292 250.9s Passed
Pipeline7 13 Solved 216 228.1s Failed
Pipeline7 14 Failed 131.9s Failed
TinyHypergraphPortPointPathingSolverPhase: portPointPathingSolver
SelectiveReripTinyHyperGraphSolverWithStableInitialAssignments ran out of iterations
Pipeline7 15 Failed 97.5s Failed
TinyHypergraphPortPointPathingSolverPhase: portPointPathingSolver
SelectiveReripTinyHyperGraphSolverWithStableInitialAssignments ran out of iterations
Pipeline7 16 Solved 100 62.7s Failed
PR run details
Solver Sample Status Via Time Relaxed DRC Error Delta
Pipeline7 1 Solved 184 (=best) 49.3s Passed
Pipeline7 2 Solved 490 374.8s Failed
Pipeline7 3 Solved 90 (=best) 47.1s Passed
Pipeline7 4 Solved 159 178.4s Failed
Pipeline7 5 Solved 143 (+40, worse) 44.6s Passed
Pipeline7 6 Solved 305 1065.8s Failed Improved
Pipeline7 7 Solved 231 (=best) 90.9s Passed
Pipeline7 8 Failed 230.9s Failed
MultipleHighDensityRouteStitchSolver3Phase: highDensityStitchSolver
AutoroutingPipelineSolver7_MultiGraph error: Error: SingleHighDensityRouteStitchSolver3 found unknown PCB terminal "pcb_port_71" on "source_trace_9__source_net_9_mst29"
Regressed
Pipeline7 9 Solved 124 85.5s Failed
Pipeline7 10 Solved 171 (=best) 222.2s Passed
Pipeline7 11 Solved 177 (-2, better) 133.0s Passed
Pipeline7 12 Solved 290 (-2, better) 359.4s Passed
Pipeline7 13 Solved 197 381.9s Failed
Pipeline7 14 Solved 296 989.1s Failed Improved
Pipeline7 15 Solved 303 519.7s Failed Improved
Pipeline7 16 Solved 97 81.8s Failed

Workflow: View run
Artifact: https://github.com/tscircuit/tscircuit-autorouter/actions/runs/32293166500

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/benchmark-long --dataset 18 --sample-timeout 7200s

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18 Failed

Benchmark workflow ended with cancelled before completion.

This can happen during setup, dependency installation, or benchmark execution.

Main vs PR

(benchmark results were not produced)

Workflow: View run
Artifact: https://github.com/tscircuit/tscircuit-autorouter/actions/runs/32313945328

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Fast failure-risk proxy result for 7fc78e6:

The selector now uses B = sum(nodePf) + 0.5 * sum(nodePf^2), the second-order negative-log-success burden, and reports P(hard search) = sigmoid(-3.528 + 1.557 * log1p(B)). The estimate costs about 8.5 ns/call in a 10M-call Bun microbenchmark and uses summaries already computed for each candidate. No downstream routing probe is run.

Validation before this run: 536 routes with leave-one-dataset-out calibration gave AUC 0.818, Brier 0.153, and log loss 0.455 for predicting >100k high-density iterations. Ranking on held-out srj18 was AUC 0.881.

Same-machine dataset 18 result: completion 87.5% -> 93.8%, relaxed DRC 43.8% -> 50.0%, no timeouts. The 10% burden-reduction gate selected optimized candidates only for samples 2, 6, 10, 13, and 15; it rejected the marginal changes for 3, 4, 9, 12, and 16. On samples solved by both main and PR, DRC issues fell 268 -> 196 (-26.9%). Total issues rose 284 -> 347 because newly completed samples 14 and 15 contribute 151 issues that were previously unmeasurable failures.

Tradeoff: this improves completion and DRC outcomes, but it is not a speed win overall: P50 +13.3%, P60 +56.5%, P95 +23.5%. The repeated run ranked hard-search cases at AUC 0.917, though that repeat is not independent of the training corpus.

Benchmark: #2152 (comment)

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/usf

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tscircuitbot commented Aug 20, 2026

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📸 Update Snapshots (focused)

✅ Snapshot updates committed to 156a7f0.

Focused test files:

  • tests/autorouting-dataset18-sample10-exact-drc-residue-visual.test.ts
  • tests/bugs/bugreport12-35ce1c.test.ts
    CI test shard: 2

Source failure run: https://github.com/tscircuit/tscircuit-autorouter/actions/runs/32327533297

Changed snapshots:

  • tests/__snapshots__/autorouting-dataset18-sample10-exact-drc-residue-visual-linux.snap.svg

Environment: benchmark runner (ARM64), Bun 1.3.8

🔗 Workflow: View run

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/usf --ubuntu-latest

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📸 Update Snapshots (focused)

✅ No snapshot changes were produced; nothing to commit.

Focused test files:

  • tests/autorouting-dataset18-sample10-exact-drc-residue-visual.test.ts
  • tests/bugs/bugreport12-35ce1c.test.ts
    CI test shard: 2

Source failure run: https://github.com/tscircuit/tscircuit-autorouter/actions/runs/32327533297

Environment: ubuntu-latest (X64), Bun 1.3.8

🔗 Workflow: View run

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This PR has been automatically marked as stale because it has had no recent activity. It will be closed if no further activity occurs.

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This PR was closed because it has been inactive for 1 day since being marked as stale.

@github-actions github-actions Bot closed this Aug 25, 2026
…hypergraph-166-region-cost

# Conflicts:
#	lib/solvers/PortPointPathingSolver/tinyhypergraph/TinyHypergraphPortPointPathingSolver.ts
#	package.json
#	tests/__snapshots__/autorouting-dataset18-sample10-exact-drc-residue-visual-linux.snap.svg
@seveibar seveibar reopened this Aug 26, 2026
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/benchmark-long --same-machine --pipeline 7 --dataset 18 --sample-timeout 7200s

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/benchmark-long --same-machine --pipeline 9 --dataset 18 --sample-timeout 7200s

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tscircuitbot commented Aug 26, 2026

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Same Machine Benchmark Results

Both revisions ran sequentially in one Blacksmith job on blacksmith-01m0zrt08qk9fe7045b0rp49q4-8vcpu.

Dataset: srj18 · Scenarios: 16
Main: c642eac · PR: f28dd3e

Solver Metric Main PR Delta
Pipeline9 Completion 87.5% 87.5% 0.0 pp
Pipeline9 Relaxed DRC pass 50.0% 50.0% 0.0 pp
Pipeline9 DRC issues 171 143 -28
Pipeline9 Timeouts 0 0 0
Pipeline9 P50 time 107.7s 126.7s +17.7%
Pipeline9 P60 time 135.2s 138.7s +2.6%
Pipeline9 P70 time 232.5s 260.8s +12.2%
Pipeline9 P80 time 273.3s 356.9s +30.6%
Pipeline9 P90 time 381.9s 480.1s +25.7%
Pipeline9 P95 time 487.4s 618.3s +26.9%
Pipeline9 Average vias 213.64 212.50 -0.5%

Outcome changes: 0 improved, 0 regressed. DRC issues are totaled across solved samples. Timing percentiles include solved and timed-out samples; negative timing deltas are faster.

Workflow: View run
Artifact: Download raw reports

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Same Machine Benchmark Results

Both revisions ran sequentially in one Blacksmith job on blacksmith-01m0zrt02mteredqbtmx5csdm3-8vcpu.

Dataset: srj18 · Scenarios: 16
Main: c642eac · PR: f28dd3e

Solver Metric Main PR Delta
Pipeline7 Completion 87.5% 87.5% 0.0 pp
Pipeline7 Relaxed DRC pass 43.8% 43.8% 0.0 pp
Pipeline7 DRC issues 221 131 -90
Pipeline7 Timeouts 0 0 0
Pipeline7 P50 time 118.0s 126.5s +7.2%
Pipeline7 P60 time 124.3s 185.0s +48.8%
Pipeline7 P70 time 191.8s 234.1s +22.1%
Pipeline7 P80 time 242.0s 327.0s +35.1%
Pipeline7 P90 time 312.8s 330.7s +5.7%
Pipeline7 P95 time 437.5s 515.9s +17.9%
Pipeline7 Average vias 217.36 212.50 -2.2%

Outcome changes: 0 improved, 0 regressed. DRC issues are totaled across solved samples. Timing percentiles include solved and timed-out samples; negative timing deltas are faster.

Workflow: View run
Artifact: Download raw reports

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This PR has been automatically marked as stale because it has had no recent activity. It will be closed if no further activity occurs.

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This PR was closed because it has been inactive for 1 day since being marked as stale.

@github-actions github-actions Bot closed this Aug 31, 2026
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