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Add buses configuration to chip props - #840

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feat/chip-buses
Open

Add buses configuration to chip props#840
seveibar wants to merge 2 commits into
mainfrom
feat/chip-buses

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@seveibar seveibar commented Sep 9, 2026

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Allow chips to declare routing buses with buses?: ChipBusProps<PinLabel>[]. Each declaration uses local pinNames; core can resolve those pins to connections when creating a <bus /> element.

<chip
  name="U1"
  buses={[
    {
      name: "DATA",
      pinNames: ["D0", "D1"],
      maxLengthSkew: "0.5mm",
      targetImpedance: "50ohm",
    },
  ]}
/>

Derive the chip bus schema from busProps, replacing connections with a nonempty pinNames array. Reuse all routing options, validation, and unit conversion. Pin names use schematic pin label validation and are constrained to known pins when using typed ChipProps. Standalone bus props retain connections.

Omission and an empty buses array declare no buses; no aliases or implicit merges are added. This PR supplies the props contract; resolving local pins and creating bus elements remains a core implementation step.

Validation: 513 tests pass, including nested parsing, unit conversion, invalid declarations, optional/empty buses, required pinNames, and compile-time pin-name validation. Type checking, formatting, build, and all required generation scripts pass.

Comment thread tests/chip-buses.test.ts
Comment on lines +1 to +60
import { expect, test } from "bun:test"
import { busProps, chipProps, type ChipProps } from "lib"

test("chip bus declarations use standalone bus parsing", () => {
const props: ChipProps = {
name: "U1",
buses: [
{
name: "DATA",
connections: [".U1 > .D0", ".U1 > .D1"],
maxLengthSkew: "500um",
targetImpedance: "50ohm",
pcbTraceWidth: "0.2mm",
pcbAllowedLayers: ["top", "bottom"],
preferredLayer: "top",
preferredLayers: ["top", "bottom"],
routingPhaseIndex: 1,
},
{ connections: ["RESET"], routingPhaseIndex: null },
],
}
const parsed = chipProps.parse(props)
expect(parsed.buses).toEqual(props.buses!.map((bus) => busProps.parse(bus)))
expect(parsed.buses?.[0]?.maxLengthSkew).toBe(0.5)
expect(parsed.buses?.[0]?.targetImpedance).toBe(50)
expect(parsed.buses?.[0]?.pcbTraceWidth).toBe(0.2)
})

test("chip buses are optional and may be empty", () => {
expect(chipProps.parse({ name: "U1" }).buses).toBeUndefined()
expect(chipProps.parse({ name: "U1", buses: [] }).buses).toEqual([])
})

test("chip rejects invalid nested bus declarations", () => {
for (const bus of [
{},
{ connections: [] },
{ connections: [1] },
{ connections: ["DATA"], maxLengthSkew: "-1mm" },
{ connections: ["DATA"], targetImpedance: 0 },
{ connections: ["DATA"], pcbTraceWidth: 0 },
{ connections: ["DATA"], pcbAllowedLayers: [] },
{ connections: ["DATA"], preferredLayers: [] },
]) {
const result = chipProps.safeParse({ name: "U1", buses: [bus] })
expect(result.success).toBe(false)
if (!result.success) {
expect(result.error.issues[0]?.path.slice(0, 2)).toEqual(["buses", 0])
}
}
})

test("chip buses require connections at compile time", () => {
const props: ChipProps = {
name: "U1",
// @ts-expect-error Each bus requires connections.
buses: [{ name: "DATA" }],
}
void props
})

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This file contains 4 test(...) calls (at lines 4, 29, 34, and 53), but the rule states that a *.test.ts file may have AT MOST one test(...). The file should be split into multiple numbered files, e.g., chip-buses1.test.ts, chip-buses2.test.ts, chip-buses3.test.ts, and chip-buses4.test.ts, each containing exactly one test(...) call.

Spotted by Graphite (based on custom rule: Custom rule)

Fix in Graphite


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