Fix dense mixed-width boundary fanouts without size thresholds - #235
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Fix dense mixed-width boundary fanouts without size thresholds#235ShiboSoftwareDev wants to merge 1 commit into
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Dataset 31 — AM62L, RK3308, K230, i.MX6ULL, T113-S3, and AM3352 fanout benchmarkCommit: Full JSON/Markdown reports and logs Solved 29/72 selected samples. Completed 72/72; partial 0; errors 0; timeouts 43. Concurrency: 32; per-sample deadline: 120s; assignment budget: sample defaults. Only dataset-fanout31-am62l is benchmarked: 12 AM62L, 12 RK3308, 12 K230, 12 i.MX6ULL, 12 T113-S3, and 12 AM3352 cases. A case is solved only when all its SoC connections have validated fanout with the original constraints (135 for AM62L; 162 for RK3308; 171 for K230; 102 for i.MX6ULL; 128 for T113-S3; 322 for AM3352). RAM fanout and inter-chip routing are separate phases. Dataset revision: Per-sample results
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Dataset 31 — AM62L, RK3308, K230, i.MX6ULL, T113-S3, and AM3352 fanout benchmarkCommit: Full JSON/Markdown reports and logs Solved 27/72 selected samples. Completed 72/72; partial 0; errors 0; timeouts 45. Concurrency: 32; per-sample deadline: 120s; assignment budget: sample defaults. Only dataset-fanout31-am62l is benchmarked: 12 AM62L, 12 RK3308, 12 K230, 12 i.MX6ULL, 12 T113-S3, and 12 AM3352 cases. A case is solved only when all its SoC connections have validated fanout with the original constraints (135 for AM62L; 162 for RK3308; 171 for K230; 102 for i.MX6ULL; 128 for T113-S3; 322 for AM3352). RAM fanout and inter-chip routing are separate phases. Dataset revision: Per-sample results
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PR #232 solves the exact AM62L DDR4 repro, but its new dense-boundary path is selected by fixed bus and connection-count limits. Those limits make the strategy depend on input size rather than the routing conflict it handles.
This replaces that policy with a structural trigger for boundary-only layouts where separate atomic bus fields compete with singleton corridors. The solver reserves every first via jointly, routes multi-connection buses before singleton corridors in physical target order, and tries the next atomic bus when the first ordered candidate cannot route. Existing mixed boundary/plane behavior keeps its established policy and route geometry.
Source-corner normalization now reruns length matching only when repaired geometry actually violates a declared bus or differential-pair constraint. The repro from #231 and its passing DRC/SVG assertions remain unchanged.
Validation:
bun run typecheckbun run format:checkbun test— 308 pass, 0 fail, 634,799 assertions on the threshold-free solver tree