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Route sparse BGA boundary escapes through vacant grid sites - #158

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codex/repro-am625sip-sparse-bga-fanoutfrom
codex/fix-sparse-bga-dogbone-sites
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Route sparse BGA boundary escapes through vacant grid sites#158
AnasSarkiz wants to merge 2 commits into
codex/repro-am625sip-sparse-bga-fanoutfrom
codex/fix-sparse-bga-dogbone-sites

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@AnasSarkiz

@AnasSarkiz AnasSarkiz commented Sep 5, 2026

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B21/MMC1_DAT1 in the AM625SiP reproduction now escapes through a legal neighboring vacant grid site. The case improves from 2/3 to 3/3 connections with one through-all via and zero connectivity or copper DRC issues.

Stacked on #157, which contains the unchanged captured input, report, debugger page, and before snapshot. Review/land #157 first; this PR targets its branch to keep the reproduction and fix separate.

The boundary-route search now enumerates neighboring ball-grid positions within one pitch of each source. It accepts only straight/45-degree source stubs, validates every proposed site through the existing dogbone matcher, and validates complete route plans against the original obstacles and accepted copper. Candidate coordinates participate in the static-clearance cache key. Existing directional handedness/order candidates remain first. Occupied grid positions are discarded before matching; legal vacant-site candidates are computed once per bus routing call and reused across route-order attempts. The extra search is skipped when there are no usable vacant sites. No chip-specific routing coordinates, manual traces, via-in-pad, changed clearances, or router substitution are used. Existing component-wide/plane matching is unchanged.

The reproduction regression now requires 3/3 connectivity and independent copper DRC with one via. An additional visual regression places a bottom-layer pad at the vacant site and requires the solve to fail, demonstrating through-all clearance enforcement. The outer-row control and existing nine-bus AM62L PCB snapshot remain unchanged.

PCB snapshots

Before (#157):

Before: 2/3

After:

After: 3/3

Blocked bottom-layer site:

Blocked via site

Validation

bun run typecheck
bun run format:check
bun run build:site
bun test tests/am625sip-microsd-fanout-repro.test.ts tests/am625sip-microsd-fanout-control.test.ts tests/am625sip-microsd-blocked-vacancy.test.ts tests/component-dogbone-via-site-matching.test.ts
bun test tests/am62l-lpddr4-progressive-through-all-soc-repro.test.ts

All listed checks pass (6 focused tests plus the unchanged AM62L snapshot). All 12 directional exit settings were also checked: each solves 3/3 with no copper DRC issues. The five tests that exposed extra-search overhead now pass locally at their unchanged deadlines, alongside the three AM625SiP regressions (8/8 pass). GitHub CI at 25fe730 passes all 8 test shards, aggregate tests, and the preview build; no checks remain pending or failed. Typecheck and formatting also pass locally (the repository runs those CI workflows only for PRs targeting main).

The canonical dataset31 benchmark completed at the exact fix commit 25fe730, using the default 4 workers and 120-second sample deadline:

Result Baseline b859939 Fix 25fe730
Solved samples 1/12 1/12
Timed-out samples 11/12 11/12
Errors / partial results 0 / 0 0 / 0
Left-center sample connectivity 135/135 135/135

The broader AM62L benchmark remains deadline-limited; these timeouts are not successful solves. Local runs had different background load, so this comparison does not establish a speedup. The AM625SiP regression is independently verified at 3/3, including all 12 directional exit settings.

This fixes native fanout prefix generation only. The downstream circuit remains configured for Pipeline 9.

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Project Deployment Actions Updated
fanout-solver Ready Ready Preview Sep 5, 2026 1:19pm UTC

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@seveibar

seveibar commented Sep 5, 2026

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/benchmark

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