Fix build exit status for circuit errors while retaining artifacts - #4715
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Builds containing circuit errors now exit 1 and count affected circuits as failed, while retaining generated artifacts and reporting “Build completed with errors.” Artifact generation still completes before the final exit status is applied. Warnings and explicitly ignored errors continue to exit 0.
Adds regression coverage for serial and parallel builds, mixed passing/failing circuits, warnings, ignored errors, and retention of circuit JSON and PCB SVG output. Updates existing DRC expectations.
Validation: 9 regression tests pass (34 assertions, 2 snapshots); CLI build, formatting checks, and
git diff --checkpass.Fixes #4707.