Build software better, together

google / skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

magic asic eda pdk asic-library openroad openram skywater

Updated Jul 21, 2026
Python

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Mar 25, 2026
Python

efabless / caravel

Star

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys caravel picorv32 openroad vexriscv openram sky130

Updated Feb 26, 2025
Verilog

efabless / caravel_mpw-one

Star

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys caravel picorv32 openroad openram sky130

Updated Feb 22, 2022
Verilog

ShonTaware / SRAM_SKY130

Star

Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns

openram sky130 sram-memories

Updated May 2, 2021
SourcePawn

SinaKarvandi / hardware-design-stack

Star

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

asic fpga vhdl chisel chisel3 verilog vivado gtkwave modelsim netlist verilator vivado-hls asic-design vitis openram openlane vitis-hls

Updated Oct 8, 2023
VHDL

ranaumarnadeem / autoMBIST

Star

Open-source MBIST, BIRA and BISR generator for OpenRAM memories, taken through RTL-to-GDS on sky130 with LibreLane

Updated Oct 18, 2026
Python

Kishor5115 / SkyForge-RISCV-SoC

Star

Production-quality RV32IM SoC built on PicoRV32 — FreeRTOS port, UVM verification, JTAG debug, and full ASIC tapeout flow on SkyWater sky130.

asic gpio riscv debug freertos spi uart systemverilog soc jtag picorv32 openram openlane embdedded skywater-sky130

Updated Jul 13, 2026
Jupyter Notebook

rahul-shahtp / Pipelined-32-bit-RISCV-processor

Star

A complete RTL-to-GDS implementation of a 5-stage pipelined RISC-V RV32IM processor (base integer ISA + M-extension for multiply/divide) in Verilog. Features full ALU forwarding, hazard detection with load-use stalls, early branch resolution, iterative MUL/DIV/REM unit, and byte/halfword/word memory ops. Verified with 16/16 SystemVerilog regression

verilog vlsi risc-v riscv32 vlsi-design openroad openram

Updated Sep 11, 2026
Verilog

PeraMorphIQ / PeraMorphIQ-SRAM-Compiler

Star

A robust, automated SRAM compiler workflow based on OpenRAM. Features fixes for modern Python/Numpy environments, automated multi-bank generation, and Synopsys (DB/NDM) post-processing.

vlsi-design hardware-generation openram sram-compiler memory-generator

Updated Aug 21, 2026
Jupyter Notebook

siarch / openram_sky130_memories

Star

SKY130 SRAM generation, real-area closure, multi-tool output organization, and delivery packaging for 1RW and 1R1W memories.

asic eda sram delivery physical-design openram sky130 memory-generator 1rw 1r1w

Updated Jun 27, 2026
SourcePawn

WaffleBits / heterocore-memory

Star

HeteroCore component: SRAM hierarchy model and OpenRAM config generator

python hardware sram memory-hierarchy openram

Updated Jun 14, 2026
Python

devduttkadale1 / AI-Assisted-4KB-SRAM-SKY130_devdutt_kadale

Star

AI-Assisted 4KB SRAM Design using OpenRAM and SKY130 PDK

asic eda sram vlsi physical-design memory-design openram sky130 ai-assisted-engineering opensource-silicon

Updated Sep 6, 2026
SourcePawn

ShahabuddinDanish / riscv-lite-processor

Star

5-stage pipelined RISC-V (RV32I subset) processor in SystemVerilog that runs compiled C through variable-latency memories over an OBI-style request/ready protocol. Full ASIC flow: Synopsys DC synthesis at 641 MHz and Cadence Innovus place & route on NanGate 45 nm, plus OpenRAM SSRAM integration.

systemverilog computer-architecture vlsi questasim logic-synthesis risc-v rv32i processor-design asic-design place-and-route rtl-design synopsys-dc openram hardware-design cadence-innovus pipelined-processor nangate45

Updated Oct 18, 2026
SystemVerilog

Navigation Menu

openram

Here are 14 public repositories matching this topic...

google / skywater-pdk

The-OpenROAD-Project / OpenLane

efabless / caravel

efabless / caravel_mpw-one

ShonTaware / SRAM_SKY130

SinaKarvandi / hardware-design-stack

ranaumarnadeem / autoMBIST

Kishor5115 / SkyForge-RISCV-SoC

rahul-shahtp / Pipelined-32-bit-RISCV-processor

PeraMorphIQ / PeraMorphIQ-SRAM-Compiler

siarch / openram_sky130_memories

WaffleBits / heterocore-memory

devduttkadale1 / AI-Assisted-4KB-SRAM-SKY130_devdutt_kadale

ShahabuddinDanish / riscv-lite-processor

Add this topic to your repo