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Add WIPESWR/NOWIPESWR configuration. Add post-EEPROM write delay.
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Tom Seddon committed Feb 9, 2025
1 parent 8b793d2 commit 88dc0a9
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18 changes: 17 additions & 1 deletion docs/refresh.md
Original file line number Diff line number Diff line change
Expand Up @@ -121,6 +121,9 @@ together, so the version numbers for all 3 variants stay in sync.
are more similar internally
* 3.20F, 3.50F: add Tube power-on boot delay to accommodate slower
PiTube startup time
* 3.50F: add `WIPESWR`/`NOWIPESWR` configuration options
* 3.50F: add experimental mitigations for EEPROMs that become
unresponsive when written to

### safe mode

Expand Down Expand Up @@ -158,7 +161,7 @@ ignored.
You may also see this if you use 3rd-party tools designed for the B/B+
that disable ROMs by modifying the ROM information table.

### Tube power-on boot delay
### Tube power-on boot delay (3.20/3.50 only)

The MOS can wait longer on initial power up for the 2nd processor to
become ready, to accomodate PiTube startup time when it's powered by
Expand All @@ -176,6 +179,19 @@ you'll be waiting for the full period.)
The delay is ignored when `*CONFIGURE NOTUBE`, and always applies to
power-on reest only.

### retain sideways RAM on power-on reset (3.50 only)

MOS 3.50 erase sideways RAM if it detects a power-on reset. This is
now configurable.

`*CONFIGURE WIPESWR` (shown as `Wipe SWR` in the `*STATUS` output),
the default, will erase sideways RAM on a power-on reset. This is the
Acorn MOS 3.50 behaviour.

`*CONFIGURE NOWIPESWR` (shown as `No Wipe SWR` in the `*STATUS`
output) will leave sideways RAM contents alone on a power-on reset -
the behaviour for other Acorn MOS versions.

## E

No code changes, but prebuilt full MegaROM images are now included in
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12 changes: 10 additions & 2 deletions src/configure_table_driven.s65
Original file line number Diff line number Diff line change
Expand Up @@ -40,12 +40,12 @@ Sbyte2: .macro value,value350
; The RTC byte indexes in the table are actually
; offset.
.if !refreshVersion&&version<500
; The possible range is 1-17. A bit wasteful as bytes
; The possible range is 1-16. A bit wasteful as bytes
; 1-4 are set by ANFS. Though perhaps the original
; intention was for the MOS to manage them.
metadataRTCByteIndexOffset=cmosBytesOffset+CMOSBytes.fileServerStationNumber
.else
; The possible range is 5-21.
; The possible range is 5-20.
metadataRTCByteIndexOffset=cmosBytesOffset+CMOSBytes.defaultROMs
.endif

Expand Down Expand Up @@ -165,6 +165,9 @@ lastNoDirChar:=noDir.metadata-1
.if includeTubeSupport
.itemWithMetadata "NoTube",CMOSBytes.defaults2,CMOSBytes.defaults2.tubeOnMask,0,false
.endif
.if refreshVersion&&version==350
noWipeSWR: .itemWithMetadata "NoWipeSWR",CMOSBytes.defaults3,CMOSBytes.defaults3.noWipeSWR,1,false
.endif
print: .itemWithMetadata "Print",CMOSBytes.defaults2,CMOSBytes.defaults2.fx5SettingMask<<CMOSBytes.defaults2.fx5SettingShift,0,true
.itemWithMetadata "Quiet",CMOSBytes.defaults3,CMOSBytes.defaults3.loudMask,0,false
.itemWithMetadata "Repeat",CMOSBytes.keyboardAutoRepeatRate,$ff,0,true
Expand All @@ -187,6 +190,9 @@ lastShChar=shCaps+1
.itemWithMetadata "Stick",CMOSBytes.joystick,CMOSBytes.joystick.stickMask,0,true
.endif
.itemWithAddress "TV",handleTV
.if refreshVersion&&version==350
.itemWithMetadata "WipeSWR",CMOSBytes.defaults3,CMOSBytes.defaults3.noWipeSWR,0,false
.endif
; Terminator for data-driven table
.byte 0

Expand All @@ -210,6 +216,8 @@ tubeDelayMetadata:
.itemMetadata $00,CMOSBytes.defaults4,CMOSBytes.defaults4.tubePowerOnDelayMask<<CMOSBytes.defaults4.tubePowerOnDelayShift,0,true
.endif

.cerror *-configureTable>=256,"configureTable is too large"

.endif

; Text snippets.
Expand Down
36 changes: 36 additions & 0 deletions src/mos.s65
Original file line number Diff line number Diff line change
Expand Up @@ -13981,6 +13981,42 @@ LFB3B:

.endif

;-------------------------------------------------------------------------
;
; Delay after a possible EEPROM write, to give the device time to time
; out out of write mode. Trying to stay reasonably under 10 ms. Don't
; interfere with the 100 Hz timer, but give the 100 Hz routine at
; least a bit of time to run.
;
; 256 times round inner loop=2+256*2+255*3+2=1281 cycles
;
; 1281 cycles = 0.6405 ms
;
; 12 iterations = 15372+(a bit) cycles=~7.7 ms
;
; This can be revisited if required.
;
; Preserves: A/X/P

.if version==350&&refreshVersion
delayAfterPossibleEEPROMWrite: .proc
php
pha
sei
ldy #12
outerLoop:
lda #0
innerLoop:
inc a
bne innerLoop
dey
bne outerLoop
pla
plp
rts
.endproc
.endif

;-------------------------------------------------------------------------

mosUnusedBegin:
Expand Down
7 changes: 7 additions & 0 deletions src/mos_workspace.s65
Original file line number Diff line number Diff line change
Expand Up @@ -1875,6 +1875,10 @@ fx5SettingShift=5

defaults3: .block
.fill 1
.if version==350
; Annoying backwards naming so that 0 means wipe.
noWipeSWR=1
.endif
loudMask=2
.if includeTubeSupport
extTubeMask=4
Expand Down Expand Up @@ -1915,7 +1919,10 @@ defaults4: .block
tubePowerOnDelayMask=15 ; max 15 seconds
tubePowerOnDelayShift=4
.endblock

.endif


.endstruct

.if refreshVersion
Expand Down
33 changes: 26 additions & 7 deletions src/reset.s65
Original file line number Diff line number Diff line change
Expand Up @@ -52,31 +52,50 @@
.if version==350
bne nonPowerOnReset
jsr resetCRTC
.if refreshVersion
jsr selectTerminalROM
jsr clearTSTAndReadDefaults3
and #CMOSBytes.defaults3.noWipeSWR
bne startClearRAM ; taken if *CONFIGURE NOWIPESWR
.endif
ldx #7

LFC34:
clearSidewaysRAMLoop:
jsr selectROMX
ldy #$80 ; ''
sty 1
stz 0
tay

LFC3E:
clearSidewaysRAMBankLoop:
sta (0),y
iny
bne LFC3E
bne clearSidewaysRAMBankLoop
inc 1
bit 1
bvc LFC3E
bvc clearSidewaysRAMBankLoop
dex
cpx #4
bcs LFC34
bcs clearSidewaysRAMLoop

.if refreshVersion
; the same delay should cover all banks
jsr delayAfterPossibleEEPROMWrite
.endif

jsr selectTerminalROM
tya

.if refreshVersion

startClearRAM:
ldy #$00

.else

tya
startClearRAM:
tay

.endif
LFC53:
ldx TEMPA
tya
Expand Down
21 changes: 21 additions & 0 deletions src/sram_access_helpers_2.s65
Original file line number Diff line number Diff line change
Expand Up @@ -73,13 +73,34 @@ isBankROM:
eor #$ff
sei
sta $8008 ; store modified value

.if version==350&&refreshVersion

jsr delayAfterPossibleEEPROMWrite
cmp $8008 ; did it take? Z=1 if RAM
clc ; assume ROM

; Don't do another write if ROM, in case it's EEPROM
; and it'll only make another mess.
bne jmpSelectTerminalROM ; taken if ROM
sec ; it's RAM
sty $8008 ; it's RAM - restore original
; value
jmpSelectTerminalROM:
cli
jmp selectTerminalROM

.else

cmp $8008 ; did it take? Z=1 if RAM
sty $8008 ; restore original value
cli
beq jmpSelectTerminalROM ; taken if RAM
clc
jmpSelectTerminalROM:
jmp selectTerminalROM
.endif


;-------------------------------------------------------------------------

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