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SoundWire: add support for link clock source selection #4605
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plbossart
merged 8 commits into
thesofproject:topic/sof-dev
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plbossart:sdw/mlcs-support
Jan 3, 2024
Merged
SoundWire: add support for link clock source selection #4605
plbossart
merged 8 commits into
thesofproject:topic/sof-dev
from
plbossart:sdw/mlcs-support
Jan 3, 2024
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SOFCI TEST |
"This PR should not be merged until the firmware issue is better understood." It's been 2 weeks and no one looked into this, so let's go ahead and review/merge this capability which does provide the 12 MHz support needed for additional SoundWire work. |
RanderWang
approved these changes
Oct 9, 2023
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LGTM
bardliao
previously approved these changes
Oct 11, 2023
SOFCI TEST |
…ontroller Existing DSDT or SSDT platforms hard-code clock and frame shape configurations. For validation, we'd like to use alternate configurations. It's not always possible to generate new tables due to missing symbols, and modifying existing objects usually leads to AE_OBJECT_EXIST errors. The mechanism suggested in this patch is to add a NEW ACPI controller device with a different _ADR value. e.g. Scope (_SB_.PC00.RP08.PXSX.HDAS) { Device (SDWP) { Name (_ADR, 0x40000001) // _ADR: Address The desired _ADR can be passed as a parameter with options snd-intel-sdw-acpi sdw_ctrl_addr=0x40000001 This solution leads to minimal tables with just what the developers or validation engineers need, and without overriding any of the existing firmware definitions. It's consistent with the recommendation to extend ACPI definitions and not redefine them with a risk of conflict. Signed-off-by: Pierre-Louis Bossart <[email protected]>
This log is useful when trying different configurations, specifically to make sure ACPI initrd overrides have been taken into account. Signed-off-by: Pierre-Louis Bossart <[email protected]>
Starting with MeteorLake, the input frequency to the SoundWire IP can be 96MHz. The existing code is limited to 24MHz, change accordingly and move branch after the 32MHz case to avoid issues. While we're at it, reorder the frequencies by increasing order. Signed-off-by: Pierre-Louis Bossart <[email protected]>
Starting with MeteorLake, the input to the SoundWire IP can be 24.576 MHz (aka Audio Cardinal Clock) or 96 MHz (Audio PLL). Signed-off-by: Pierre-Louis Bossart <[email protected]>
In the MeteorLake hardware, the SoundWire link clock can be selected from the Xtal, audio cardinal clock (24.576 MHz) or the 96 MHz audio PLL. This patches add the clock selection in a backwards-compatible manner, using the ACPI firmware as the source of information and checking its compatibility with hardware capabilities. Signed-off-by: Pierre-Louis Bossart <[email protected]>
The input clock to the SoundWire IP can be 38.4 MHz (xtal clock source) 24.576 MHz (audio cardinal clock) 96 MHz (internal Audio PLL) This patch moves the clock selection outside the mutex and add the new choices for 24.576 and 96 MHz, but doesn't add any functionality. Follow-up patches will add support for clock selection. Signed-off-by: Pierre-Louis Bossart <[email protected]>
The existing sequence is fine if we want to only use the xtal clock. However if we want to select the clock, we first need to power-up, then select the clock and last set the SYNCPRD. This patch first modifies the order, we will add the clock selection as a follow-up. Signed-off-by: Pierre-Louis Bossart <[email protected]>
Insert clock setup after power-up and before setting up the SYNCPRD, per hardware recommendations. Signed-off-by: Pierre-Louis Bossart <[email protected]>
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bardliao
approved these changes
Dec 19, 2023
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Since CannonLake, we've been using the XTAL oscillator as the link clock source, but since MeteorLake the hardware offers two additional sources: the audio cardinal clock and the internal audio PLL.
Tested on MTL RVP and LNL RVP, with scripts in thesofproject/acpi-scripts#20
One issue was reported for 12.288MHz, the playback is 2x too slow and this is root-caused to a firmware change thesofproject/sof#8251
This PR should not be merged until the firmware issue is better understood.
@bardliao @kv2019i FYI