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@valpackett
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(Continues #11)

TODO:

  • implement flash latency management directly in RCC (?) instead of the dp.FLASH.acr fiddling in the USB example /* RM0038 3.3.1 */
  • figure out the "correct" USB startup_delay72 copy-pasted from F1 does just work but may be excessive?
  • hide the apb1 fiddling in USB enable into functions like other HALs do: USB::enable_unchecked() etc. (how do they do that?)

This was referenced Jan 10, 2022
@hdhoang
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hdhoang commented Jan 13, 2022

Thank you! I will try to find some time to run examples on my keyboard. USB support is essential

@hdhoang
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hdhoang commented Jun 25, 2022

thanks for porting it to rtic@1 as well! I'm working through their examples again.

The usage of .write() was disabling the PLL's source (!) exactly
when the PLL itself was enabled, causing the PLL to never come up.
24 is not a real restriction: anything above 16 requires
setting LATENCY (1 WS) for flash already.
32 is when the flash maxes out even in LATENCY mode.
Mostly based on the other STM32 HALs
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3 participants