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Add regression test for undriven net initialisation (issue #1041).
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4 files changed

+77
-0
lines changed

4 files changed

+77
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lines changed

ivtest/vpi/br_gh1041.c

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#include <vpi_user.h>
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static PLI_INT32 start_cb(struct t_cb_data *cb)
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{
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static struct t_vpi_value val;
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vpiHandle wire;
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(void)cb; // suppress unused parameter warning
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wire = vpi_handle_by_name("test.w4", NULL);
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if (wire) {
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val.format = vpiIntVal;
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val.value.integer = 1;
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vpi_put_value(wire, &val, NULL, vpiNoDelay);
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} else {
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vpi_printf("Failed to get handle for w4\n");
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}
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wire = vpi_handle_by_name("test.w8", NULL);
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if (wire) {
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val.format = vpiIntVal;
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val.value.integer = 1;
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vpi_put_value(wire, &val, NULL, vpiNoDelay);
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} else {
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vpi_printf("Failed to get handle for w8\n");
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}
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wire = vpi_handle_by_name("test.wr", NULL);
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if (wire) {
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val.format = vpiRealVal;
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val.value.real = 1.0;
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vpi_put_value(wire, &val, NULL, vpiNoDelay);
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} else {
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vpi_printf("Failed to get handle for wr\n");
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}
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return 0;
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}
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static void register_cb(void)
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{
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struct t_cb_data cbd = {};
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cbd.reason = cbStartOfSimulation;
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cbd.cb_rtn = start_cb;
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vpi_register_cb(&cbd);
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}
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void (*vlog_startup_routines[])(void) = {
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register_cb,
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0
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};

ivtest/vpi/br_gh1041.v

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module test;
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wire w4;
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tri0 w8;
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wire real wr;
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reg failed = 0;
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initial begin
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#0;
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$display("w4 %b w8 %b wr %f", w4, w8, wr);
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if (w4 !== 1'b1) failed = 1;
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if (w8 !== 1'b1) failed = 1;
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if (wr != 1.0) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule

ivtest/vpi_gold/br_gh1041.gold

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Compiling vpi/br_gh1041.c...
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Making br_gh1041.vpi from br_gh1041.o...
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w4 1 w8 1 wr 1.000000
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PASSED

ivtest/vpi_regress.list

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@@ -71,6 +71,7 @@ br_gh308 normal br_gh308.c br_gh308.gold
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br_gh317 normal br_gh317.c br_gh317.gold
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br_gh496 normal,-g2009 br_gh496.c br_gh496.gold
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br_gh1037 normal,-g2009 br_gh1037.c br_gh1037.gold
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br_gh1041 normal br_gh1041.c br_gh1041.gold
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br_ml20191013 normal br_ml20191013.c br_ml20191013.gold
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by_index normal by_index.c by_index.gold
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by_name normal by_name.c by_name.log

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