@@ -969,14 +969,21 @@ void input_connect(vvp_net_t*fdx, unsigned port, char*label)
969969
970970 vvp_vector4_t tmp = c4string_to_vector4 (label);
971971
972- // Inputs that are constants are schedule to execute as
972+ // Inputs that are constants are scheduled to execute as
973973 // soon at the simulation starts. In Verilog, constants
974974 // start propagating when the simulation starts, just
975975 // like any other signal value. But letting the
976976 // scheduler distribute the constant value has the
977977 // additional advantage that the constant is not
978978 // propagated until the network is fully linked.
979- schedule_set_vector (ifdx, tmp);
979+ // For constants that initialise an undriven net, we
980+ // schedule execution before time 0, to make sure it
981+ // occurs before any sensitive processes are started
982+ // or VPI callbacks are executed.
983+ if (label[0 ] == ' c' )
984+ schedule_init_vector (ifdx, tmp);
985+ else
986+ schedule_set_vector (ifdx, tmp);
980987
981988 free (label);
982989 return ;
@@ -986,7 +993,10 @@ void input_connect(vvp_net_t*fdx, unsigned port, char*label)
986993 if (c8string_test (label)) {
987994
988995 vvp_vector8_t tmp = c8string_to_vector8 (label);
989- schedule_set_vector (ifdx, tmp);
996+ if (label[0 ] == ' c' )
997+ schedule_init_vector (ifdx, tmp);
998+ else
999+ schedule_set_vector (ifdx, tmp);
9901000
9911001 free (label);
9921002 return ;
@@ -998,7 +1008,10 @@ void input_connect(vvp_net_t*fdx, unsigned port, char*label)
9981008
9991009 double tmp = crstring_to_double (label);
10001010
1001- schedule_set_vector (ifdx, tmp);
1011+ if (label[0 ] == ' c' )
1012+ schedule_init_vector (ifdx, tmp);
1013+ else
1014+ schedule_set_vector (ifdx, tmp);
10021015 free (label);
10031016 return ;
10041017 }
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