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2 changes: 1 addition & 1 deletion src/Ice40/IO.hs
Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,7 @@ import Data.String.Interpolate.Util (unindent)
|]) #-}

-- | IO primitive, see io for wrapper
{-# NOINLINE ioPrim #-}
{-# OPAQUE ioPrim #-}
ioPrim
:: BitVector 6 -- ^ pinType
-> Bit -- ^ pullup
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2 changes: 1 addition & 1 deletion src/Ice40/Led.hs
Original file line number Diff line number Diff line change
Expand Up @@ -79,7 +79,7 @@ import Data.String.Interpolate.Util (unindent)
]
|]) #-}

{-# NOINLINE ledPrim #-}
{-# OPAQUE ledPrim #-}
ledPrim
:: Signal dom Bit -- ARG[0] leddcs - CS to write LEDD IP registers
-> Clock dom -- ARG[1] leddclk - Clock to write LEDD IP registers
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2 changes: 1 addition & 1 deletion src/Ice40/Mac/Prim.hs
Original file line number Diff line number Diff line change
Expand Up @@ -134,7 +134,7 @@ import Data.String.Interpolate.Util (unindent)
|]) #-}

-- | Multiply-Accumulate primitive
{-# NOINLINE macPrim #-}
{-# OPAQUE macPrim #-}
macPrim
:: Bit -- ^ negTrigger
-> Bit -- ^ aReg
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2 changes: 1 addition & 1 deletion src/Ice40/Osc.hs
Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,7 @@ lf10kHz !_ !_ = Clock SSymbol Nothing
]
|]) #-}

{-# NOINLINE hfPrim #-}
{-# OPAQUE hfPrim #-}
hfPrim
:: KnownDomain dom -- ARG[0]
=> KnownDomain dom' -- ARG[1]
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2 changes: 1 addition & 1 deletion src/Ice40/Rgb.hs
Original file line number Diff line number Diff line change
Expand Up @@ -88,7 +88,7 @@ import Data.String.Interpolate.Util (unindent)
-- +-----------------------+-------------------+-------------------+
-- | "0b111111" | 24mA | 12mA |
-- +-----------------------+-------------------+-------------------+
{-# NOINLINE rgbPrim #-}
{-# OPAQUE rgbPrim #-}
rgbPrim
:: String -- ^ currentMode - Parameter values: "0b0" = Full Current Mode (Default), "0b1" = Half Current Mode.
-> String -- ^ rgb0Current
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2 changes: 1 addition & 1 deletion src/Ice40/Spi.hs
Original file line number Diff line number Diff line change
Expand Up @@ -227,7 +227,7 @@ bitAt n = fmap (! n)
]
|]) #-}

{-# NOINLINE spiPrim #-}
{-# OPAQUE spiPrim #-}
spiPrim
:: String -- ARG[0] busAddr
-> Clock dom -- ARG[1] sbclki
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2 changes: 1 addition & 1 deletion src/Ice40/Spram.hs
Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@ import Data.String.Interpolate.Util (unindent)
data Nyb = Nyb3 | Nyb2 | Nyb1 | Nyb0

-- | Single port RAM primitive
{-# NOINLINE spramPrim #-}
{-# OPAQUE spramPrim #-}
spramPrim
:: KnownDomain dom -- ARG[0]
=> Clock dom -- ^ clock
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