VoltageSource: Create DCGenerator only if special setParameters is us…

…ed and not always when the frequency is 0. This should avoid any regressions. Signed-off-by: Niklas Eiling <[email protected]>
sogno-platform · Aug 21, 2024 · 5f40f09 · 5f40f09
1 parent 6f98d0e
commit 5f40f09
Show file tree

Hide file tree

Showing 4 changed files with 27 additions and 16 deletions.
diff --git a/dpsim-models/include/dpsim-models/DP/DP_Ph1_VoltageSource.h b/dpsim-models/include/dpsim-models/DP/DP_Ph1_VoltageSource.h
@@ -80,6 +80,10 @@ class VoltageSource : public MNASimPowerComp<Complex>,
   void setParameters(Complex initialPhasor, Real modulationFrequency,
                      Real modulationAmplitude, Real baseFrequency = 0.0,
                      bool zigzag = false);
+  /// Setter for reference voltage with a real valued generator
+  /// This will initialize the values of mVoltageRef to match the given parameters
+  /// However, the attributes can be modified during the simulation to dynamically change the value of the output voltage.
+  void setParameters(Real voltageRef);
 
   // #### MNA Section ####
   /// Initializes internal variables of the component

diff --git a/dpsim-models/src/DP/DP_Ph1_VoltageSource.cpp b/dpsim-models/src/DP/DP_Ph1_VoltageSource.cpp
@@ -30,21 +30,23 @@ SimPowerComp<Complex>::Ptr DP::Ph1::VoltageSource::clone(String name) {
   return copy;
 }
 
+void DP::Ph1::VoltageSource::setParameters(Real voltageRef) {
+  auto srcDC = Signal::DCGenerator::make(**mName + "_dc");
+  srcDC->mVoltageRef->setReference(mVoltageRef);
+  srcDC->setParameters(voltageRef);
+
+  mSrcSig = srcDC;
+  mParametersSet = true;
+}
+
 void DP::Ph1::VoltageSource::setParameters(Complex voltageRef, Real srcFreq) {
-  if (srcFreq == 0.0) {
-    auto srcDC = Signal::DCGenerator::make(**mName + "_dc");
-    srcDC->mVoltageRef->setReference(mVoltageRef);
-    srcDC->setParameters(voltageRef.real());
+  auto srcSigSine = Signal::SineWaveGenerator::make(**mName + "_sw");
+  srcSigSine->mVoltageRef->setReference(mVoltageRef);
+  srcSigSine->mFreq->setReference(mSrcFreq);
+  srcSigSine->setParameters(voltageRef, srcFreq);
 
-    mSrcSig = srcDC;
-  } else {
-    auto srcSigSine = Signal::SineWaveGenerator::make(**mName + "_sw");
-    srcSigSine->mVoltageRef->setReference(mVoltageRef);
-    srcSigSine->mFreq->setReference(mSrcFreq);
-    srcSigSine->setParameters(voltageRef, srcFreq);
+  mSrcSig = srcSigSine;
 
-    mSrcSig = srcSigSine;
-  }
   mParametersSet = true;
 }
 

diff --git a/dpsim-villas/examples/cxx/FpgaExample.cpp b/dpsim-villas/examples/cxx/FpgaExample.cpp
@@ -116,7 +116,7 @@ SystemTopology loopbackTopology(CommandLineArgs &args,
 
   // Components
   auto vs = VoltageSource::make("v_s");
-  vs->setParameters(Complex(10, 0), 0);
+  vs->setParameters(10.);
   auto rl = Resistor::make("r_l");
   rl->setParameters(1);
 
@@ -147,7 +147,7 @@ SystemTopology hilTopology(CommandLineArgs &args, std::shared_ptr<Interface> int
 
   // Components
   auto vs = VoltageSource::make("v_s");
-  vs->setParameters(Complex(1, 0), 50);
+  vs->setParameters(1.);
   auto rs = Resistor::make("r_s");
   rs->setParameters(1);
 

diff --git a/dpsim-villas/include/dpsim-villas/InterfaceVillasQueueless.h b/dpsim-villas/include/dpsim-villas/InterfaceVillasQueueless.h
@@ -55,8 +55,13 @@ class InterfaceVillasQueueless
   virtual void printVillasSignals() const;
 
   virtual ~InterfaceVillasQueueless() {
-    if (mOpened)
-      close();
+    if (mOpened) {
+      try {
+        close();
+      } catch (const std::exception &e) {
+        SPDLOG_LOGGER_ERROR(mLog, "Error closing interface: {}", e.what());
+      }
+    }
   }
 
 protected: