Merge pull request #1222 from slaclab/clocks-gty+

Misc. GT Clock outputs for the GTY+ ETH modules
slaclab · Jan 1, 2025 · 6c8e7e0 · 6c8e7e0
2 parents 60065b6 + 85eb2ad
commit 6c8e7e0
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Showing 2 changed files with 4 additions and 1 deletion.
diff --git a/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScaleWrapper.vhd b/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScaleWrapper.vhd
@@ -77,6 +77,7 @@ entity GigEthGtyUltraScaleWrapper is
       gtRefClk            : in  sl                                             := '0';
       gtClkP              : in  sl                                             := '1';
       gtClkN              : in  sl                                             := '0';
+      gtClkOut            : out sl;
       -- Copy of internal MMCM reference clock and Reset
       refClkOut           : out sl;
       refRstOut           : out sl;
@@ -122,7 +123,7 @@ begin
          IB    => gtClkN,
          CEB   => '0',
          ODIV2 => gtClk,
-         O     => open);
+         O     => gtClkOut);
 
    BUFG_GT_Inst : BUFG_GT
       port map (

diff --git a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd
@@ -70,6 +70,7 @@ entity XauiGtyUltraScaleWrapper is
       -- MGT Clock Port (156.25MHz or 312.5MHz)
       gtClkP             : in  sl;
       gtClkN             : in  sl;
+      gtClkOut           : out  sl;
       -- MGT Ports
       gtTxP              : out slv(3 downto 0);
       gtTxN              : out slv(3 downto 0);
@@ -88,6 +89,7 @@ architecture mapping of XauiGtyUltraScaleWrapper is
 begin
 
    phyReady <= linkUp;
+   gtClkOut <= refClk;
 
    U_refClk : IBUFDS_GTE4
       port map (