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  1. DIGITAL_VLSI_SOC_DESIGN_AND_PLANNING DIGITAL_VLSI_SOC_DESIGN_AND_PLANNING Public

  2. UVM-Test-Bench-For-APB-Protocol UVM-Test-Bench-For-APB-Protocol Public

    A UVM testbench for the APB slave.

    SystemVerilog

  3. UVM-Test-Bench-For-AXI-Bus UVM-Test-Bench-For-AXI-Bus Public