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riscv-peripheral rework #288

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Instead of using associated functions, this PR proposes using methods. The benefits of this change are:

  1. It follows the same approach as in svd2rust. Thus, the PACs using this tool will benefit from a more uniform API.
  2. It allows using the Deref trait to simplify the peripheral_codegen! macros.

I also removed the embedded-hal-async partial support. The reason for removing this is that while implementing a few asynchronous functions, I noticed that it is difficult to provide a generic and optimized implementation for any RISC-V target. Instead, I think it is more reasonable to implement a custom chip-hal-async crate that makes the most of the characteristics of a given chip.

This is still a work-in-progress PR. I want to make sure that everything works as expected by updating svd2rust and e310x.

@romancardenas romancardenas requested a review from a team as a code owner May 16, 2025 16:10
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This PR is being prevented from merging because it presents one of the blocking labels: work in progress, do not merge.

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This PR is being prevented from merging because it presents one of the blocking labels: work in progress, do not merge.

@romancardenas romancardenas force-pushed the riscv-peripheral-rework branch from 3145c81 to 66026e1 Compare May 16, 2025 16:14
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