Add transactional SPI

Cargo.toml

@@ -7,6 +7,7 @@ license = "MIT OR Apache-2.0"
 name = "linux-embedded-hal"
 repository = "https://github.com/japaric/linux-embedded-hal"
 version = "0.3.0"
+edition = "2018"
 
 [features]
 gpio_sysfs = ["sysfs_gpio"]
@@ -15,7 +16,7 @@ gpio_cdev = ["gpio-cdev"]
 default = [ "gpio_cdev", "gpio_sysfs" ]
 
 [dependencies]
-embedded-hal = "=1.0.0-alpha.1"
+embedded-hal = "=1.0.0-alpha.3"
 gpio-cdev = { version = "0.3", optional = true }
 sysfs_gpio = { version = "0.5", optional = true }
 
@@ -32,3 +33,4 @@ openpty = "0.1.0"
 # we don't need the `Error` implementation
 default-features = false
 version = "0.2.2"
+

src/lib.rs

@@ -13,7 +13,6 @@
 #![deny(missing_docs)]
 
 extern crate cast;
-extern crate core;
 extern crate embedded_hal as hal;
 pub extern crate i2cdev;
 pub extern crate nb;
@@ -202,7 +201,10 @@ impl hal::blocking::i2c::WriteRead for I2cdev {
         buffer: &mut [u8],
     ) -> Result<(), Self::Error> {
         self.set_address(address)?;
-        let mut messages = [LinuxI2CMessage::write(bytes), LinuxI2CMessage::read(buffer)];
+        let mut messages = [
+            LinuxI2CMessage::write(bytes),
+            LinuxI2CMessage::read(buffer),
+        ];
         self.inner.transfer(&mut messages).map(drop)
     }
 }
@@ -257,6 +259,38 @@ impl hal::blocking::spi::Write<u8> for Spidev {
     }
 }
 
+pub use hal::blocking::spi::{Operation as SpiOperation};
+
+/// Transactional implementation batches SPI operations into a single transaction
+impl hal::blocking::spi::Transactional<u8> for Spidev {
+    type Error = io::Error;
+
+    fn try_exec<'a>(&mut self, operations: &mut [SpiOperation<'a, u8>]) -> Result<(), Self::Error> {
+
+        // Map types from generic to linux objects
+        let mut messages: Vec<_> = operations.iter_mut().map(|a| {
+            match a {
+                SpiOperation::Write(w) => SpidevTransfer::write(w),
+                SpiOperation::Transfer(r) => {
+                    // Clone read to write pointer
+                    // SPIdev is okay with having w == r but this is tricky to achieve in safe rust
+                    let w = unsafe {
+                        let p = r.as_ptr();
+                        std::slice::from_raw_parts(p, r.len())
+                    };
+
+                    SpidevTransfer::read_write(w, r)
+                },
+            }
+        }).collect();
+
+        // Execute transfer
+        self.0.transfer_multiple(&mut messages)?;
+
+        Ok(())
+    }
+}
+
 impl ops::Deref for Spidev {
     type Target = spidev::Spidev;