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updated to match changes to https://github.com/riscv-software-src/riscv-isa-sim/blob/master/arch_test_target/spike/model_test.h

update set_msw/clear_msw/set_mtimer/clear_mtimer
Added ifndef to clint addresses instead of hard-coding Added clear_msw and clear mtimer

updated to match changes to https://github.com/riscv-software-src/riscv-isa-sim/blob/master/arch_test_target/spike/model_test.h

update set_msw/clear_msw/set_mtimer/clear_mtimer
Added ifndef to clint addresses instead of hard-coding
Added clear_msw and clear mtimer

Signed-off-by: Dan Smathers <[email protected]>
@jamesbeyond jamesbeyond changed the base branch from master to dev May 21, 2024 17:00
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