fixup! target/hexagon: Add {TLB,k0}lock, cause code, wait_next_pc #112
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Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
The BADVA reg is referred to with the wrong identifier. The CAUSE reg field of SSR is not yet modeled, we will dump the SSR in a subsequent commit. Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
…ags() Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
These registers are defined in the Qualcomm Hexagon V71 Programmer's Reference Manual - https://docs.qualcomm.com/bundle/publicresource/80-N2040-51_REV_AB_Hexagon_V71_ProgrammerS_Reference_Manual.pdf Refer to §11.9.1 SYSTEM GUEST, §11.9.2 SYSTEM MONITOR. Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
Also: add nop TCG overrides for break,unpause,fetchbo,dczeroa break: this hardware breakpoint instruction is used with the in-silicon debugger feature, this is not modeled. unpause: this instruction is used to resume hardware threads that are stalled by pause instructions. pause is modeled as a nop, or in RR mode as an EXCP_YIELD. This instruction is safe to ignore. Since cache/prefetch functions are not modeled, dczero and fetchbo are safe to ignore. Signed-off-by: Brian Cain <[email protected]>
This commit provides handlers to generate TCG for guest and system register reads and writes. They will be leveraged by a future commit. Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
Define the register fields for ssr, schedcfg, stid, bestwait, ccr, modectl, imask, ipendad. Define the fields for TLB entries. Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
Define TCG overrides for setprio(), crswap(,sgp{0,1,1:0}).
Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
Define TCG overrides for {c,}swi {c,s}iad, iassign{r,w}, {s,g}etimask
instructions.
Signed-off-by: Brian Cain <[email protected]>
Define TCG overrides for start, stop, wait, resume instructions. Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
Co-authored-by: Sid Manning <[email protected]> Signed-off-by: Brian Cain <[email protected]>
Signed-off-by: Matheus Tavares Bernardino <[email protected]>
Signed-off-by: Brian Cain <[email protected]>
Add the #if defined (TARGET_HEXAGON) to hmp-commands-info.hx Prefix each TLB entry with the index Signed-off-by: Taylor Simpson <[email protected]>
Signed-off-by: Sid Manning <[email protected]>
Signed-off-by: Marco Liebel <[email protected]>
Signed-off-by: Marco Liebel <[email protected]>
The number of parameters for `DEF_MACRO` changed and needed to be updated too. Signed-off-by: Marco Liebel <[email protected]>
Signed-off-by: Marco Liebel <[email protected]>
Signed-off-by: Marco Liebel <[email protected]>
Signed-off-by: Marco Liebel <[email protected]>
A single mapping is made by qct-qtimer.c and the extraneous region caused confusion. Signed-off-by: Sid Manning <[email protected]>
* TODO: forward the instruction tag to the unimp log? * TODO: why do we need_env() for these? * TODO: filter out some attributes? These instructions are unimplemented for now, they are used by h2.
Signed-off-by: Sid Manning <[email protected]>
Signed-off-by: Sid Manning <[email protected]>
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