Revert "Merge branch 'smazzola/chimera' into dkeller/chimera-v2"

This reverts commit 22646ae, reversing
changes made to 584f3df.

Author: DanielKellerM

.gitignore

@@ -7,3 +7,4 @@ regression_tests/
 pulp-runtime/
 fault_injection_sim/
 venv/
+.venv/

Bender.lock

@@ -98,14 +98,6 @@ packages:
       Git: https://github.com/pulp-platform/event_unit_flex.git
     dependencies:
     - common_cells
-  flex-v:
-    revision: e9355c2f6ec4c105abdff39489e5d1be93bc4374
-    version: null
-    source:
-      Git: https://github.com/pulp-platform/flex-v.git
-    dependencies:
-    - fpnew
-    - tech_cells_generic
   fpnew:
     revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315
     version: null
@@ -206,6 +198,7 @@ packages:
     - hci
     - hwpe-ctrl
     - hwpe-stream
+    - register_interface
     - zeroriscy
   obi:
     revision: c2141a653c755461ff44f61d12aeb5d99fc8e760
@@ -256,6 +249,14 @@ packages:
     - axi
     - common_cells
     - common_verification
+  riscv:
+    revision: c760db14dbd6cc3ec3b8ae8274df2eac7225bcac
+    version: null
+    source:
+      Git: https://github.com/AlSaqr-platform/riscv_nn.git
+    dependencies:
+    - fpnew
+    - tech_cells_generic
   scm:
     revision: 472f99affe44ff7b282b519c047a3cfeb35b16c6
     version: 1.2.0

Bender.yml

@@ -26,15 +26,15 @@ dependencies:
   timer_unit:             { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 }
   common_cells:           { git: "https://github.com/pulp-platform/common_cells.git", version: 1.35.0 }
   tech_cells_generic:     { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 }
-  flex-v:                 { git: "https://github.com/pulp-platform/flex-v.git", rev: astral-v1.1 }
+  riscv:                  { git: "https://github.com/AlSaqr-platform/riscv_nn.git", rev: astral-v1.0 }
   cv32e40p:               { git: "https://github.com/pulp-platform/cv32e40p.git", rev: astral-v1.0 }
   ibex:                   { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" }
   scm:                    { git: "https://github.com/pulp-platform/scm.git", rev: v1.2.0 }
   hci:                    { git: "https://github.com/pulp-platform/hci.git", rev: 5421524afca701e45a83d0f1ec47568c019e021a  } # branch: main
   register_interface:     { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.5  }
   redundancy_cells:       { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 9e31f7c6c24877eaf58279903e7a162b16c9a721 } # branch: astral-v0
   redmule:                { git: "https://github.com/pulp-platform/redmule.git", rev: astral-v1.0 }
-  neureka:                { git: "https://github.com/pulp-platform/neureka.git", rev: ff7090eb3738a5192af0f4e1499e4ed44a3041e5 } # branch: main
+  neureka:                { git: "https://github.com/pulp-platform/neureka.git", rev: astral-v1.0 }
   softex:                 { git: "https://github.com/belanoa/softex.git"       , rev: astral-v1.0 }
   obi:                    { git: "https://github.com/pulp-platform/obi.git", rev: v0.1.3 }
 
@@ -96,3 +96,4 @@ sources:
     files:
     - nonfree/gf12/sourcecode/tc_sram.sv
     - nonfree/gf12/sourcecode/tc_clk.sv
+

Makefile

@@ -14,6 +14,7 @@ endif
 
 
 BENDER ?= bender
+# BENDER ?= /local/user/dkm/Projects/pulp_cluster/bender-cust/target/debug/bender
 PYTHON ?= python3
 
 VSIM ?= $(QUESTA) vsim
@@ -45,6 +46,7 @@ endef
 ######################
 
 NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-cluster-nonfree.git
+#NONFREE_COMMIT ?= 6f5b4b5aa85b6f3ac4bbe03439dd250ab4810d80 # branch: dkeller/chimera-v2
 NONFREE_BRANCH ?= dkeller/chimera-v2
 
 nonfree-init:
@@ -208,34 +210,6 @@ gen_idma_hw:
 clean_idma_hw:
 	make -C $(IDMA_ROOT) idma_clean_all
 
-#########################
-# Hardware dependencies #
-#########################
-
-# Set dependency paths only if dependencies have already been cloned
-# This avoids running `bender checkout` at every make command
-ifeq ($(shell test -d $(ROOT_DIR)/.bender || echo 1),)
-IDMA_ROOT := $(shell $(BENDER) path idma)
-endif
-
-# Fall back to safe defaults if dependencies are not cloned yet
-IDMA_ROOT ?= .
-
-# Python requirements (version and packages) coming from iDMA repository
-gen_idma_hw: $(IDMA_ROOT)/.idma_generated
-$(IDMA_ROOT)/.idma_generated:
-	@$(PYTHON) --version >/dev/null 2>&1 || { echo "ERROR: Python not found. Python 3.8 or higher is required."; exit 1; } && \
-	$(PYTHON) -c "import sys; assert sys.version_info >= (3, 8)" || { echo "ERROR: Python version must be 3.8 or higher"; exit 1; } && \
-	rm -rf venv && $(PYTHON) -m venv venv && \
-	. venv/bin/activate && \
-	pip install --upgrade pip && \
-	pip install -r $(IDMA_ROOT)/requirements.txt && \
-	make -C $(IDMA_ROOT) idma_hw_all && \
-	touch $@
-
-clean_idma_hw:
-	make -C $(IDMA_ROOT) idma_clean_all
-
 ########################
 # Build and simulation #
 ########################

bender-common.mk

@@ -11,7 +11,6 @@ common_defs += -D CLUSTER_ALIAS
 common_defs += -D USE_PULP_PARAMETERS
 
 common_targs += -t rtl
-
 # DMA configuration
 DMA_TYPE ?= idma
 

rtl/cluster_interconnect_wrap.sv

@@ -179,7 +179,6 @@ module cluster_interconnect_wrap
           .N_MEM  ( NB_TCDM_BANKS            ),
           .IW     ( TCDM_ID_WIDTH            ),
           .TS_BIT ( TEST_SET_BIT             ),
-          .EXPFIFO ( 2                       ),
           .`HCI_SIZE_PARAM(cores) ( HCI_CORE_SIZE ),
           .`HCI_SIZE_PARAM(mems)  ( HCI_MEM_SIZE  ),
           .`HCI_SIZE_PARAM(hwpe)  ( HCI_HWPE_SIZE )

rtl/idma_wrap.sv

@@ -39,7 +39,7 @@ module dmac_wrap #(
   parameter int unsigned GLOBAL_QUEUE_DEPTH     = 2,
   // mux read ports between tcdm-tcdm and tcdm-axi?
   parameter bit          MUX_READ               = 1'b0,
-  parameter bit          TCDM_MEM2BANKS         = 1'b0,
+    parameter bit          TCDM_MEM2BANKS         = 1'b0,
   // when using mem2banks (implies AXI_DATA_WIDTH==64):
   // 4 ports per stream if read ports muxed, otherwise 6
   // when not using mem2banks:
@@ -177,7 +177,7 @@ module dmac_wrap #(
   axi_req_t  [       NumStreams-1:0] dma_req;
   axi_resp_t [       NumStreams-1:0] dma_rsp;
 
-  // interface to structs
+  // interface to structs  
   for (genvar s = 0; s < NUM_BIDIR_STREAMS; s++) begin : gen_connect_interface
     assign ext_master_req_o[s] = soc_req[s];
     assign soc_rsp[s]          = ext_master_resp_i[s];

rtl/pulp_cluster.sv

@@ -375,6 +375,7 @@ localparam DMA_IW_CONTRIB_FAC = Cfg.DmaUseHwpePort ? 0 : 1;
 // if using MCHAN, must be 32
 localparam int unsigned DMA_HCI_DATA_WIDTH = Cfg.DmaUseHwpePort ? Cfg.AxiDataOutWideWidth : DataWidth;
 
+
 localparam hci_package::hci_size_parameter_t HciCoreSizeParam = '{
   DW:  DataWidth,
   AW:  AddrWidth,
@@ -616,6 +617,7 @@ hci_core_intf #(
   c2s_out_int_req_t s_dma_narrow_master_req;   // Narrow DMA master (64-bit) 
   c2s_out_int_resp_t s_dma_narrow_master_resp;
 
+
   // core per2axi -> ext
   c2s_in_int_req_t s_core_ext_bus_req;
   c2s_in_int_resp_t s_core_ext_bus_resp;
@@ -906,6 +908,7 @@ end else begin : gen_narrow_port_idma
   );
 end
 
+
 //***************************************************
 //**************CLUSTER PERIPHERALS******************
 //***************************************************
@@ -2047,12 +2050,13 @@ if (Cfg.AxiDataInWidth != Cfg.AxiDataOutWidth) begin
   `AXI_ASSIGN_REQ_STRUCT(s_data_slave_32_req,dst_remap_req)
   `AXI_ASSIGN_RESP_STRUCT(dst_remap_resp,s_data_slave_32_resp)
 
-  axi_dw_converter #(
-    .AxiIdWidth            ( AxiIdInWidth         ),
-    .AxiAddrWidth          ( Cfg.AxiAddrWidth     ),
-    .AxiSlvPortDataWidth   ( Cfg.AxiDataInWidth   ),
-    .AxiMstPortDataWidth   ( Cfg.AxiDataOutWidth  ),
-    .AxiMaxReads           ( 1                    ),
+  axi_dw_converter_intf #(
+    .AXI_ID_WIDTH            ( AxiIdInWidth         ),
+    .AXI_ADDR_WIDTH          ( Cfg.AxiAddrWidth     ),
+    .AXI_SLV_PORT_DATA_WIDTH ( Cfg.AxiDataInWidth   ),
+    .AXI_MST_PORT_DATA_WIDTH ( Cfg.AxiDataOutWidth  ),
+    .AXI_USER_WIDTH          ( Cfg.AxiUserWidth     ),
+    .AXI_MAX_READS           ( 1                    ),
     .aw_chan_t               ( s2c_in_int_aw_chan_t ),
     .mst_w_chan_t            ( c2s_w_chan_t         ),
     .slv_w_chan_t            ( s2c_in_int_w_chan_t  ),
@@ -2128,6 +2132,9 @@ initial begin : p_assert
     assert(DMA_HCI_DATA_WIDTH == DataWidth)
       else $fatal(1, "When Cfg.DmaUseHwpePort is 0, DMA_HCI_DATA_WIDTH must be equal to DataWidth!");
   end
+  // Note: iDMA now uses conditional data width and AXI path selection
+  // EnableWidePort=0: iDMA uses 64-bit narrow transfers via cluster bus AXI path  
+  // EnableWidePort=1: iDMA uses 256-bit wide transfers via dedicated wide AXI path
   `endif
 end
 `endif

tb/pulp_cluster_tb.sv

@@ -494,14 +494,6 @@ module pulp_cluster_tb;
     .AXI_USER_WIDTH ( AxiUw ),
     .LOG_DEPTH      ( 3     )
   ) async_cluster_to_soc_axi_bus();
-  
-  AXI_BUS_ASYNC_GRAY #(
-    .AXI_ADDR_WIDTH ( AxiAw    ),
-    .AXI_DATA_WIDTH ( DmaAxiDw ),
-    .AXI_ID_WIDTH   ( DmaAxiIw ),
-    .AXI_USER_WIDTH ( AxiUw    ),
-    .LOG_DEPTH      ( 3        )
-  ) async_dma_axi_bus();
 
    // Behavioural slaves
    axi_m_req_t  axi_memreq;
@@ -510,38 +502,6 @@ module pulp_cluster_tb;
   `AXI_ASSIGN_TO_REQ(axi_memreq, axi_master[1])
   `AXI_ASSIGN_FROM_RESP(axi_master[1], axi_memrsp)
 
-  axi_dw_converter_intf #(
-    .AXI_ID_WIDTH            ( AxiIw    ),
-    .AXI_ADDR_WIDTH          ( AxiAw    ),
-    .AXI_SLV_PORT_DATA_WIDTH ( DmaAxiDw ),
-    .AXI_MST_PORT_DATA_WIDTH ( AxiDw    ),
-    .AXI_USER_WIDTH          ( AxiUw    ),
-    .AXI_MAX_READS           ( 3        )
-  ) i_dma_dw_conv (
-    .clk_i  ( s_clk        ),
-    .rst_ni ( s_rstn       ),
-    .slv    ( dma_slave_iw ),
-    .mst    ( axi_slave[2] )
-  );
-
-  axi_iw_converter_intf #(
-    .AXI_SLV_PORT_ID_WIDTH        ( DmaAxiIw ),
-    .AXI_MST_PORT_ID_WIDTH        ( AxiIw    ),
-    .AXI_SLV_PORT_MAX_UNIQ_IDS    ( 5        ),
-    .AXI_SLV_PORT_MAX_TXNS_PER_ID ( 5        ),
-    .AXI_SLV_PORT_MAX_TXNS        ( 5        ),
-    .AXI_MST_PORT_MAX_UNIQ_IDS    ( 5        ),
-    .AXI_MST_PORT_MAX_TXNS_PER_ID ( 5        ),
-    .AXI_ADDR_WIDTH               ( AxiAw    ),
-    .AXI_DATA_WIDTH               ( DmaAxiDw ),
-    .AXI_USER_WIDTH               ( AxiUw    )
-  ) i_dma_iw_conv (
-    .clk_i  ( s_clk        ),
-    .rst_ni ( s_rstn       ),
-    .slv    ( dma_slave    ),
-    .mst    ( dma_slave_iw )
-  );
-
   axi_sim_mem #(
     .AddrWidth ( AxiAw        ),
     .DataWidth ( AxiDw        ),
@@ -845,4 +805,5 @@ module pulp_cluster_tb;
 
   end
 
+
 endmodule : pulp_cluster_tb