Skip to content

Commit 22646ae

Browse files
DanielKellerMDanielKellerM
authored
Merge branch 'smazzola/chimera' into dkeller/chimera-v2
2 parents 584f3df + d41ca84 commit 22646ae

File tree

9 files changed

+88
-31
lines changed

9 files changed

+88
-31
lines changed

‎.gitignore‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,4 +7,3 @@ regression_tests/
77
pulp-runtime/
88
fault_injection_sim/
99
venv/
10-
.venv/

‎Bender.lock‎

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,14 @@ packages:
9898
Git: https://github.com/pulp-platform/event_unit_flex.git
9999
dependencies:
100100
- common_cells
101+
flex-v:
102+
revision: e9355c2f6ec4c105abdff39489e5d1be93bc4374
103+
version: null
104+
source:
105+
Git: https://github.com/pulp-platform/flex-v.git
106+
dependencies:
107+
- fpnew
108+
- tech_cells_generic
101109
fpnew:
102110
revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315
103111
version: null
@@ -198,7 +206,6 @@ packages:
198206
- hci
199207
- hwpe-ctrl
200208
- hwpe-stream
201-
- register_interface
202209
- zeroriscy
203210
obi:
204211
revision: c2141a653c755461ff44f61d12aeb5d99fc8e760
@@ -249,14 +256,6 @@ packages:
249256
- axi
250257
- common_cells
251258
- common_verification
252-
riscv:
253-
revision: c760db14dbd6cc3ec3b8ae8274df2eac7225bcac
254-
version: null
255-
source:
256-
Git: https://github.com/AlSaqr-platform/riscv_nn.git
257-
dependencies:
258-
- fpnew
259-
- tech_cells_generic
260259
scm:
261260
revision: 472f99affe44ff7b282b519c047a3cfeb35b16c6
262261
version: 1.2.0

‎Bender.yml‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -26,15 +26,15 @@ dependencies:
2626
timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 }
2727
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.35.0 }
2828
tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 }
29-
riscv: { git: "https://github.com/AlSaqr-platform/riscv_nn.git", rev: astral-v1.0 }
29+
flex-v: { git: "https://github.com/pulp-platform/flex-v.git", rev: astral-v1.1 }
3030
cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: astral-v1.0 }
3131
ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" }
3232
scm: { git: "https://github.com/pulp-platform/scm.git", rev: v1.2.0 }
3333
hci: { git: "https://github.com/pulp-platform/hci.git", rev: 5421524afca701e45a83d0f1ec47568c019e021a } # branch: main
3434
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.5 }
3535
redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 9e31f7c6c24877eaf58279903e7a162b16c9a721 } # branch: astral-v0
3636
redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: astral-v1.0 }
37-
neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: astral-v1.0 }
37+
neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: ff7090eb3738a5192af0f4e1499e4ed44a3041e5 } # branch: main
3838
softex: { git: "https://github.com/belanoa/softex.git" , rev: astral-v1.0 }
3939
obi: { git: "https://github.com/pulp-platform/obi.git", rev: v0.1.3 }
4040

@@ -96,4 +96,3 @@ sources:
9696
files:
9797
- nonfree/gf12/sourcecode/tc_sram.sv
9898
- nonfree/gf12/sourcecode/tc_clk.sv
99-

‎Makefile‎

Lines changed: 28 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,6 @@ endif
1414

1515

1616
BENDER ?= bender
17-
# BENDER ?= /local/user/dkm/Projects/pulp_cluster/bender-cust/target/debug/bender
1817
PYTHON ?= python3
1918

2019
VSIM ?= $(QUESTA) vsim
@@ -46,7 +45,6 @@ endef
4645
######################
4746

4847
NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-cluster-nonfree.git
49-
#NONFREE_COMMIT ?= 6f5b4b5aa85b6f3ac4bbe03439dd250ab4810d80 # branch: dkeller/chimera-v2
5048
NONFREE_BRANCH ?= dkeller/chimera-v2
5149

5250
nonfree-init:
@@ -210,6 +208,34 @@ gen_idma_hw:
210208
clean_idma_hw:
211209
make -C $(IDMA_ROOT) idma_clean_all
212210

211+
#########################
212+
# Hardware dependencies #
213+
#########################
214+
215+
# Set dependency paths only if dependencies have already been cloned
216+
# This avoids running `bender checkout` at every make command
217+
ifeq ($(shell test -d $(ROOT_DIR)/.bender || echo 1),)
218+
IDMA_ROOT := $(shell $(BENDER) path idma)
219+
endif
220+
221+
# Fall back to safe defaults if dependencies are not cloned yet
222+
IDMA_ROOT ?= .
223+
224+
# Python requirements (version and packages) coming from iDMA repository
225+
gen_idma_hw: $(IDMA_ROOT)/.idma_generated
226+
$(IDMA_ROOT)/.idma_generated:
227+
@$(PYTHON) --version >/dev/null 2>&1 || { echo "ERROR: Python not found. Python 3.8 or higher is required."; exit 1; } && \
228+
$(PYTHON) -c "import sys; assert sys.version_info >= (3, 8)" || { echo "ERROR: Python version must be 3.8 or higher"; exit 1; } && \
229+
rm -rf venv && $(PYTHON) -m venv venv && \
230+
. venv/bin/activate && \
231+
pip install --upgrade pip && \
232+
pip install -r $(IDMA_ROOT)/requirements.txt && \
233+
make -C $(IDMA_ROOT) idma_hw_all && \
234+
touch $@
235+
236+
clean_idma_hw:
237+
make -C $(IDMA_ROOT) idma_clean_all
238+
213239
########################
214240
# Build and simulation #
215241
########################

‎bender-common.mk‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ common_defs += -D CLUSTER_ALIAS
1111
common_defs += -D USE_PULP_PARAMETERS
1212

1313
common_targs += -t rtl
14+
1415
# DMA configuration
1516
DMA_TYPE ?= idma
1617

‎rtl/cluster_interconnect_wrap.sv‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -179,6 +179,7 @@ module cluster_interconnect_wrap
179179
.N_MEM ( NB_TCDM_BANKS ),
180180
.IW ( TCDM_ID_WIDTH ),
181181
.TS_BIT ( TEST_SET_BIT ),
182+
.EXPFIFO ( 2 ),
182183
.`HCI_SIZE_PARAM(cores) ( HCI_CORE_SIZE ),
183184
.`HCI_SIZE_PARAM(mems) ( HCI_MEM_SIZE ),
184185
.`HCI_SIZE_PARAM(hwpe) ( HCI_HWPE_SIZE )

‎rtl/idma_wrap.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ module dmac_wrap #(
3939
parameter int unsigned GLOBAL_QUEUE_DEPTH = 2,
4040
// mux read ports between tcdm-tcdm and tcdm-axi?
4141
parameter bit MUX_READ = 1'b0,
42-
parameter bit TCDM_MEM2BANKS = 1'b0,
42+
parameter bit TCDM_MEM2BANKS = 1'b0,
4343
// when using mem2banks (implies AXI_DATA_WIDTH==64):
4444
// 4 ports per stream if read ports muxed, otherwise 6
4545
// when not using mem2banks:
@@ -177,7 +177,7 @@ module dmac_wrap #(
177177
axi_req_t [ NumStreams-1:0] dma_req;
178178
axi_resp_t [ NumStreams-1:0] dma_rsp;
179179

180-
// interface to structs
180+
// interface to structs
181181
for (genvar s = 0; s < NUM_BIDIR_STREAMS; s++) begin : gen_connect_interface
182182
assign ext_master_req_o[s] = soc_req[s];
183183
assign soc_rsp[s] = ext_master_resp_i[s];

‎rtl/pulp_cluster.sv‎

Lines changed: 6 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -375,7 +375,6 @@ localparam DMA_IW_CONTRIB_FAC = Cfg.DmaUseHwpePort ? 0 : 1;
375375
// if using MCHAN, must be 32
376376
localparam int unsigned DMA_HCI_DATA_WIDTH = Cfg.DmaUseHwpePort ? Cfg.AxiDataOutWideWidth : DataWidth;
377377

378-
379378
localparam hci_package::hci_size_parameter_t HciCoreSizeParam = '{
380379
DW: DataWidth,
381380
AW: AddrWidth,
@@ -617,7 +616,6 @@ hci_core_intf #(
617616
c2s_out_int_req_t s_dma_narrow_master_req; // Narrow DMA master (64-bit)
618617
c2s_out_int_resp_t s_dma_narrow_master_resp;
619618

620-
621619
// core per2axi -> ext
622620
c2s_in_int_req_t s_core_ext_bus_req;
623621
c2s_in_int_resp_t s_core_ext_bus_resp;
@@ -908,7 +906,6 @@ end else begin : gen_narrow_port_idma
908906
);
909907
end
910908

911-
912909
//***************************************************
913910
//**************CLUSTER PERIPHERALS******************
914911
//***************************************************
@@ -2050,13 +2047,12 @@ if (Cfg.AxiDataInWidth != Cfg.AxiDataOutWidth) begin
20502047
`AXI_ASSIGN_REQ_STRUCT(s_data_slave_32_req,dst_remap_req)
20512048
`AXI_ASSIGN_RESP_STRUCT(dst_remap_resp,s_data_slave_32_resp)
20522049

2053-
axi_dw_converter_intf #(
2054-
.AXI_ID_WIDTH ( AxiIdInWidth ),
2055-
.AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ),
2056-
.AXI_SLV_PORT_DATA_WIDTH ( Cfg.AxiDataInWidth ),
2057-
.AXI_MST_PORT_DATA_WIDTH ( Cfg.AxiDataOutWidth ),
2058-
.AXI_USER_WIDTH ( Cfg.AxiUserWidth ),
2059-
.AXI_MAX_READS ( 1 ),
2050+
axi_dw_converter #(
2051+
.AxiIdWidth ( AxiIdInWidth ),
2052+
.AxiAddrWidth ( Cfg.AxiAddrWidth ),
2053+
.AxiSlvPortDataWidth ( Cfg.AxiDataInWidth ),
2054+
.AxiMstPortDataWidth ( Cfg.AxiDataOutWidth ),
2055+
.AxiMaxReads ( 1 ),
20602056
.aw_chan_t ( s2c_in_int_aw_chan_t ),
20612057
.mst_w_chan_t ( c2s_w_chan_t ),
20622058
.slv_w_chan_t ( s2c_in_int_w_chan_t ),
@@ -2132,9 +2128,6 @@ initial begin : p_assert
21322128
assert(DMA_HCI_DATA_WIDTH == DataWidth)
21332129
else $fatal(1, "When Cfg.DmaUseHwpePort is 0, DMA_HCI_DATA_WIDTH must be equal to DataWidth!");
21342130
end
2135-
// Note: iDMA now uses conditional data width and AXI path selection
2136-
// EnableWidePort=0: iDMA uses 64-bit narrow transfers via cluster bus AXI path
2137-
// EnableWidePort=1: iDMA uses 256-bit wide transfers via dedicated wide AXI path
21382131
`endif
21392132
end
21402133
`endif

‎tb/pulp_cluster_tb.sv‎

Lines changed: 40 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -494,6 +494,14 @@ module pulp_cluster_tb;
494494
.AXI_USER_WIDTH ( AxiUw ),
495495
.LOG_DEPTH ( 3 )
496496
) async_cluster_to_soc_axi_bus();
497+
498+
AXI_BUS_ASYNC_GRAY #(
499+
.AXI_ADDR_WIDTH ( AxiAw ),
500+
.AXI_DATA_WIDTH ( DmaAxiDw ),
501+
.AXI_ID_WIDTH ( DmaAxiIw ),
502+
.AXI_USER_WIDTH ( AxiUw ),
503+
.LOG_DEPTH ( 3 )
504+
) async_dma_axi_bus();
497505

498506
// Behavioural slaves
499507
axi_m_req_t axi_memreq;
@@ -502,6 +510,38 @@ module pulp_cluster_tb;
502510
`AXI_ASSIGN_TO_REQ(axi_memreq, axi_master[1])
503511
`AXI_ASSIGN_FROM_RESP(axi_master[1], axi_memrsp)
504512

513+
axi_dw_converter_intf #(
514+
.AXI_ID_WIDTH ( AxiIw ),
515+
.AXI_ADDR_WIDTH ( AxiAw ),
516+
.AXI_SLV_PORT_DATA_WIDTH ( DmaAxiDw ),
517+
.AXI_MST_PORT_DATA_WIDTH ( AxiDw ),
518+
.AXI_USER_WIDTH ( AxiUw ),
519+
.AXI_MAX_READS ( 3 )
520+
) i_dma_dw_conv (
521+
.clk_i ( s_clk ),
522+
.rst_ni ( s_rstn ),
523+
.slv ( dma_slave_iw ),
524+
.mst ( axi_slave[2] )
525+
);
526+
527+
axi_iw_converter_intf #(
528+
.AXI_SLV_PORT_ID_WIDTH ( DmaAxiIw ),
529+
.AXI_MST_PORT_ID_WIDTH ( AxiIw ),
530+
.AXI_SLV_PORT_MAX_UNIQ_IDS ( 5 ),
531+
.AXI_SLV_PORT_MAX_TXNS_PER_ID ( 5 ),
532+
.AXI_SLV_PORT_MAX_TXNS ( 5 ),
533+
.AXI_MST_PORT_MAX_UNIQ_IDS ( 5 ),
534+
.AXI_MST_PORT_MAX_TXNS_PER_ID ( 5 ),
535+
.AXI_ADDR_WIDTH ( AxiAw ),
536+
.AXI_DATA_WIDTH ( DmaAxiDw ),
537+
.AXI_USER_WIDTH ( AxiUw )
538+
) i_dma_iw_conv (
539+
.clk_i ( s_clk ),
540+
.rst_ni ( s_rstn ),
541+
.slv ( dma_slave ),
542+
.mst ( dma_slave_iw )
543+
);
544+
505545
axi_sim_mem #(
506546
.AddrWidth ( AxiAw ),
507547
.DataWidth ( AxiDw ),
@@ -805,5 +845,4 @@ module pulp_cluster_tb;
805845

806846
end
807847

808-
809848
endmodule : pulp_cluster_tb

0 commit comments

Comments
 (0)