sw: Support bare-metal SMP in software stack

[emanueleparisi]

This PR contains some modification to the Cheshire software stack to ease bare-metal SMP.
The following modifications are pushed:

• move smp_pause and smp_resume to the bootrom crt0.S file, renaming them bootrom_smp_pause and bootrom_smp_resume, to support a future implementation in C of such functionalities.
• Modify the common crt0.S so that each hart is assigned a private stack memory region and make sure every hart initializes its SP, GP, MTVEC and FPU.
• Reimplemente smp_pause and smp_resume in C, in the file smp.c, and add a SMP Hello World test application.
• Patch the ZSL so that smp_pause is called on entry and smp_resume is called before invoking the next stage.

Notice that while commit 8a65d72 modifies cheshire_bootrom.S, the changes do not affect the generated .sv file, and should be hardware-neutral. I double-checked that by computing the SHA256 digest of the cheshire_bootrom.sv file in the main branch, and at commit 53d71de after regenerating it by running make chs-bootrom-all with the active toolchain pointing to riscv64-unknown-elf-gcc-12.2.0. In both cases, I obtain 6ccbbc2d958008b1d9101100bcef9dd934545623d94ed329794d37bb47919606

[paulsc96]

To be superseded by #170.