Ara integration in Cheshire (1) by mp-17 · Pull Request #112 · pulp-platform/cheshire

mp-17 · 2024-03-13T15:28:56Z

This is the first PR for Ara's support. See #160 for OS support. #160 is sufficiently stable to boot Linux with Ara.

Add bare-metal Ara to Cheshire.

Add Ara dependency to Bender and bump CVA6.
Integrate Ara in cheshire_soc. The current configuration can host a 2-lane Ara without performance degradations.
Ara can be enabled or disabled with the corresponding configuration switch with a parameter. Two parameters configure the Ara instance (AraNrLanes to determine the number of vector lanes and VLEN to determine the bit width of a single vector register).
The FPGA flow implements Cheshire without Ara.

EDIT:
PR moved to #231, to integrate CVA6 version pulp-v2.

MarekPikula · 2024-05-16T19:06:16Z

Hi, I noticed that there are multiple Ara/Cheshire/MMU-related branches. I wanted to evaluate Ara with Linux, but for that to work, I suppose that it requires proper MMU support. Since Cheshire is supposed to run Linux, I wonder if this PR has Ara MMU support. I noticed that in Bender config, it refers to branches that don't include MMU patches from the mp/chs-ara branch.

Could you let me know if there is any working setup to make Ara work with Linux (with MMU support)? I can see that there are multiple branches (i.e., mp/chs-ara, rebase/mp/chs-ara, and the original @MaistoV fork), but it's not clear to me which of these is the most "current". Did you test it in simulation or in FPGA?

mp-17 · 2024-05-17T07:38:10Z

Hello @MarekPikula,

We are internally working on a version of Ara that supports Linux on FPGA, which we plan to release in the next months gradually. The version that can now boot Linux is a bit messy and needs clean-up.
Nevertheless, if you are interested and not afraid of the mess, there is something on GitHub as well:

As a note: this is not what you see in this PR.

MarekPikula · 2024-05-17T09:39:58Z

Nice, thank you for the pointers to the right places. I tested it in FireSim on an AWS F1 FPGA, and it seems to be working fine. I haven't run any extensive tests or benchmarks yet, only some small testing algorithms I had at hand, but man, it is exciting.

Point to open-source deps - 1

krabo0om · 2024-08-26T10:35:57Z

Hi, @mp-17 thanks for the effort integrating ARA! How close is the current PR to be merged? Can we use this PR as-is on an FPGA with Linux?

mp-17 · 2024-08-26T12:00:49Z

Hello @krabo0om,

I will soon rework this PR and write down how to use Ara on FPGA since we have reached a sufficiently stable version.

MarekPikula · 2024-09-09T16:54:48Z

Hi @mp-17, today I was trying to update my FireSim setup with the updated Ara (from the master branch) but stumbled upon the following synthesis error from Vivado:

[Synth 8-2105] illegal cast operation

For the following lines:

If I remove the vlen_t'(...) cast, it gets synthesized without error (or warning), but I guess it's not really a good idea to do this without understanding what exactly causes the error. I have the new VLEN parameter initialized, so I'm at a loss as to what could cause this error. Did you encounter anything similar during your work towards FPGA compatibility?

mp-17 · 2024-09-16T08:07:48Z

Hello @MarekPikula,

can the problem be linked to the fact that vlen_t depends on VLEN, which we now pass as a parameter? (it was from an included package before)

It's an ugly fix, but if you include VLEN from a package, the error should go away. Let me know.

fulcrum34 · 2024-10-08T07:21:51Z

Hello @mp-17
Following the information in cheshire's mp/chs-ara, I was able to build cheshire-ara for genesys2 but seems its too big for it.
I tried removing VGA, DMA, GPIO, VIO, ILA but without much gains.
Below is the utilization report for Genesys2 with default config.
Config NrLanes = 2
VLEN = 2048 (1024 per lane as in ara.mk)

Just want to ask, What am I missing here? Should disabling vector FPU be of any help?

mp-17 · 2024-10-10T13:57:50Z

Hello @fulcrum34. We have only tried it on the VCU128, not yet on the Genesys2 board. You can try removing the FPUs and see if it fits.

fulcrum34 · 2024-10-11T05:03:30Z

Hello @fulcrum34. We have only tried it on the VCU128, not yet on the Genesys2 board. You can try removing the FPUs and see if it fits.

Hi, Thanks!
Yes I tried with FPUSupportNone and it fits easily but I have trouble getting it to boot linux or run baremetal.
I have also worked a version with FPU but unsupported single Lane config (pulp-platform/ara#75) to fit in.
Another thing I noticed, 200MHz clock for dram_wrapper does'nt meet timing. I used 100Mhz to be safe but I believe we can go a bit higher.

I can connect using Openocd. See openocd.log and gdb.log but the uart terminal despite correct port and baud prints ?????
The linux image does'nt boot nor does show up anything in the uart console.
Not sure what am I missing...
Once I reach a fix, I will release a PR. Hope it will help people out there with genesys2.
Good day!!! 🙂

paulsc96 · 2024-10-11T16:03:53Z

Bender.yml

  common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",           version: 1.33.0 }
  common_verification:      { git: "https://github.com/pulp-platform/common_verification.git",    version: 0.2.0  }
-  cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: pulp-v1.0.0 }
+  cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: pulp-v1    }


It is better to make new release here; pointing to a moving branch head is not a good idea.

I have released a second PR that will have tagged commits on main branches.

paulsc96

Thanks for this PR (sorry for the stray comment above).

Generally speaking, there is nothing to fundamentally object to, but some fundamental things must be done before merging:

Add the new feature and its parameters to the documentation
Add the new feature to some FPGA config and have it tested somehow in internal CI
Discuss how it constrains overall parameterization (we should do this offline).

paulsc96 · 2024-10-11T16:04:24Z

Bender.yml

  common_verification:      { git: "https://github.com/pulp-platform/common_verification.git",    version: 0.2.0  }
-  cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: pulp-v1.0.0 }
+  cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: pulp-v1    }
+  ara:                      { git: "https://github.com/pulp-platform/ara.git",                    rev: mp/cva6-pulpv1/rebase }


This should also be merged and get a release before merging this PR.

I have released a second PR that will have tagged commits on main branches.

cheshire.mk

hw/cheshire_pkg.sv

paulsc96 · 2024-10-11T16:06:44Z

hw/cheshire_pkg.sv

+      RVV                   : cfg.Ara,
      RVC                   : 1,
-      RVH                   : 1,
+      RVH                   : ~cfg.Ara,


If there are complex parameterization constraints affecting the rest of the system (which is okay generally), we need to talk these over offline and document them carefully.

Yes, we can discuss this offline!

hw/cheshire_soc.sv

mp-17 · 2025-06-24T07:38:56Z

PR moved to #231, to integrate CVA6 version pulp-v2.

mp-17 self-assigned this Mar 13, 2024

mp-17 force-pushed the mp/ara-pulpv1 branch from 54a30bb to af706dd Compare June 11, 2024 12:16

mp-17 force-pushed the mp/ara-pulpv1 branch 2 times, most recently from a814e99 to 5a3ce5d Compare July 3, 2024 16:18

mp-17 force-pushed the mp/ara-pulpv1 branch from 5a3ce5d to e646384 Compare July 10, 2024 09:49

Aquaticfuller pushed a commit that referenced this pull request Jul 16, 2024

Merge pull request #112 from pulp-platform/aottaviano/open-source

f5102f9

Point to open-source deps - 1

mp-17 force-pushed the mp/ara-pulpv1 branch from e646384 to 3f5ba53 Compare August 26, 2024 14:07

mp-17 force-pushed the mp/ara-pulpv1 branch 4 times, most recently from d214d1d to 41dbd1b Compare October 10, 2024 13:44

mp-17 force-pushed the mp/ara-pulpv1 branch from 41dbd1b to 923967a Compare October 10, 2024 17:22

mp-17 added 4 commits October 11, 2024 11:44

Bender: add Ara dependency

4002f27

hw: add Ara in RTL

be1ecaa

target/sim: add Ara test configuration

d264014

cheshire.mk: bump nonfree ref to test Ara

a4a9476

mp-17 force-pushed the mp/ara-pulpv1 branch from 4dd127c to a4a9476 Compare October 11, 2024 09:46

mp-17 marked this pull request as ready for review October 11, 2024 13:22

mp-17 requested review from CyrilKoe and paulsc96 October 11, 2024 13:23

paulsc96 reviewed Oct 11, 2024

View reviewed changes

paulsc96 requested changes Oct 11, 2024

View reviewed changes

mp-17 changed the title ~~Ara integration in Cheshire~~ Ara integration in Cheshire (1) Oct 15, 2024

mp-17 mentioned this pull request Oct 15, 2024

Ara integration in Cheshire (2) #160

Closed

fulcrum34 mentioned this pull request Oct 20, 2024

[HW/SW] Cheshire integration - Linux on FPGA pulp-platform/ara#319

Merged

3 tasks

mp-17 added 2 commits October 22, 2024 15:09

hw: 🎨 adjust vertical alignment

fc5dc4f

hw: add AraParMemReq parametrization

6a5cb03

mp-17 force-pushed the mp/ara-pulpv1 branch from abfd1ce to 2440da9 Compare October 22, 2024 13:16

mp-17 marked this pull request as draft October 22, 2024 13:26

mp-17 force-pushed the mp/ara-pulpv1 branch from 2440da9 to 6170122 Compare October 22, 2024 13:29

mp-17 added 3 commits October 22, 2024 18:50

hw: Fix parameter label

f23088b

docs: Add Ara to docs

4db04de

cheshire.mk: Shorten the nonfree hash

dc79fa1

mp-17 force-pushed the mp/ara-pulpv1 branch from 6170122 to dc79fa1 Compare October 22, 2024 16:50

mp-17 closed this Jun 24, 2025

Conversation

mp-17 commented Mar 13, 2024 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

This is the first PR for Ara's support. See #160 for OS support. #160 is sufficiently stable to boot Linux with Ara.

Uh oh!

MarekPikula commented May 16, 2024

Uh oh!

mp-17 commented May 17, 2024

Uh oh!

MarekPikula commented May 17, 2024

Uh oh!

krabo0om commented Aug 26, 2024

Uh oh!

mp-17 commented Aug 26, 2024

Uh oh!

MarekPikula commented Sep 9, 2024

Uh oh!

mp-17 commented Sep 16, 2024 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

fulcrum34 commented Oct 8, 2024

Uh oh!

mp-17 commented Oct 10, 2024

Uh oh!

fulcrum34 commented Oct 11, 2024 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

paulsc96 Oct 11, 2024 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Choose a reason for hiding this comment

Uh oh!

mp-17 Oct 22, 2024

Choose a reason for hiding this comment

Uh oh!

paulsc96 left a comment • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Choose a reason for hiding this comment

Uh oh!

paulsc96 Oct 11, 2024

Choose a reason for hiding this comment

Uh oh!

mp-17 Oct 22, 2024

Choose a reason for hiding this comment

Uh oh!

Uh oh!

Uh oh!

paulsc96 Oct 11, 2024

Choose a reason for hiding this comment

Uh oh!

mp-17 Oct 22, 2024

Choose a reason for hiding this comment

Uh oh!

Uh oh!

Uh oh!

Uh oh!

mp-17 commented Jun 24, 2025

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

5 participants

mp-17 commented Mar 13, 2024 •

edited

Loading

mp-17 commented Sep 16, 2024 •

edited

Loading

fulcrum34 commented Oct 11, 2024 •

edited

Loading

paulsc96 Oct 11, 2024 •

edited

Loading

paulsc96 left a comment •

edited

Loading