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chaoqun-liang
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alex96295
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Bender.lock
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| - common_verification | ||
| - register_interface | ||
| - tech_cells_generic | ||
| axi_mem_if: |
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This is added because the dependency is in pulp-ethernet, please remove it as from my review (https://github.com/pulp-platform/pulp-ethernet/pull/3/files#r1500435712), it should not be needed.
| SpiHost : 1, | ||
| Gpio : 1, | ||
| Dma : 1, | ||
| Dma : 0, |
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I know this is WIP, but make sure you test correct working of the ethernet integration when the system DMA is enabled. Just a reminder :)
hw/cheshire_soc.sv
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| output logic eth_txck_o, | ||
| output logic [3:0] eth_txd_o, | ||
| output logic eth_txctl_o, | ||
| output logic eth_rstn_o, |
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As the lint action on github suggests, there are some trailing spaces. Please remove trailing spaces before pushing
hw/cheshire_soc.sv
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| .reg_rsp_o ( reg_out_rsp[RegOut.ethernet] ) // req from cheshire def, but inside ethernet, it awaits for the type | ||
| ); | ||
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| end else begin : gen_no_ethernet |
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Since the port is incoming into the crossbar, req is an input and resp is an output. Tie input to '0 and leave outputs floating
| @@ -0,0 +1,72 @@ | |||
| #include <stdio.h> | |||
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Missing license + autorship
target/sim/src/tb_cheshire_pkg.sv
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| function automatic cheshire_cfg_t gen_cheshire_rt_cfg(); | ||
| cheshire_cfg_t ret = DefaultCfg; | ||
| ret.AxiRt = 1; | ||
| ret.AxiRt = 0; |
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It should work when AxiRt is enabled, same reminder as for the system DMA :)
| # Default on fast simulation flags. | ||
| if {![info exists VOPTARGS]} { | ||
| set VOPTARGS "-O5 +acc=p+tb_cheshire_soc. +noacc=p+cheshire_soc. +acc=r+stream_xbar" | ||
| set VOPTARGS "-O5 +acc=p+tb_cheshire_soc. +acc=p+cheshire_soc. +acc=r+stream_xbar" |
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Please do not upstream these changes, keep them local or set VOPTARGS when locally running the simulation :) let the default as is now
| .reg_req_t ( reg_req_t ), | ||
| .reg_rsp_t ( reg_rsp_t ) | ||
| ) i_tx_eth_idma_wrap ( | ||
| .clk_i, |
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Suggestion: Update the ethernet here with the version with exposed clocks; this is important so that we can handle clock generation in Cheshire
@thommythomaso do you think we should handle clock generation for ethernet in cheshire, or expose these clocks also in cheshire and let the end user provide the correct clock? In the latter case, we can generate them in the cheshire testbench as for cheshire's main clock
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* target/sim: Add JTAG tasks to read/write 32b registers * target/sim: Add JTAG task to halt and load binary Can be used by platforms to halt CVA6 and preload a shared memory when execution happens on domains different than Cheshire. * target/sim: Clean up added tasks --------- Co-authored-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>
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@thommythomaso @alex96295
axi-rt,idma)idmaregs updatepulp-ethernetintegration