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debug(runtime): isolate KV260-only Stage1 GEMM store/wedge
agent-safeSafe for AI agent: wiring, tests, scripts, docs, or scaffolding.Safe for AI agent: wiring, tests, scripts, docs, or scaffolding.area:gemmGEMM systolic array, DSP W4A8 MAC, packing, or recovery.GEMM systolic array, DSP W4A8 MAC, packing, or recovery.area:kv260Kria KV260 board specificsKria KV260 board specificsarea:memoryMemory hierarchyMemory hierarchyarea:npu-topTop-level NPU wiring, status, memory routing, or E2E path.Top-level NPU wiring, status, memory routing, or E2E path.area:softwareBare-metal SW, HAL, instruction emitter, polling, or weights.Bare-metal SW, HAL, instruction emitter, polling, or weights.area:verificationSimulation, testbench, golden model, or xsim verification.Simulation, testbench, golden model, or xsim verification.priority:P1Next milestone blockerNext milestone blockerstatus:in-progressActively being workedActively being workedtype:bugReproducible defectReproducible defecttype:testTest or testbench workTest or testbench workStatus: Open.docs/admin: audit contributor onboarding after first external PR
agent-safeSafe for AI agent: wiring, tests, scripts, docs, or scaffolding.Safe for AI agent: wiring, tests, scripts, docs, or scaffolding.area:adminExternal application, license, access, funding, or artifact policy.External application, license, access, funding, or artifact policy.priority:P2Planned but not blockingPlanned but not blockingstatus:readyTriaged and actionableTriaged and actionabletype:docsDocumentation-only changeDocumentation-only changeStatus: Open.- Status: Open.#147 In pccxai/pccx-FPGA-NPU-LLM-kv260;
[P1][EVIDENCE] Collect and organize v0.2.0 release evidence
area:verificationSimulation, testbench, golden model, or xsim verification.Simulation, testbench, golden model, or xsim verification.priority:P1Next milestone blockerNext milestone blockerstatus:readyTriaged and actionableTriaged and actionabletype:docsDocumentation-only changeDocumentation-only changeStatus: Open.[EPIC] v002 correctness, bring-up, and hardware closure tracking
area:adminExternal application, license, access, funding, or artifact policy.External application, license, access, funding, or artifact policy.area:specArchitecture, ISA, scale policy, or data format.Architecture, ISA, scale policy, or data format.priority:P1Next milestone blockerNext milestone blockerstatus:in-progressActively being workedActively being workedtype:docsDocumentation-only changeDocumentation-only changeStatus: Open.[P1][CVO] Add CVO/SFU function and softmax-path testbench
area:cvoCVO/SFU, CORDIC, softmax, RoPE, or nonlinear scalar ops.CVO/SFU, CORDIC, softmax, RoPE, or nonlinear scalar ops.human-review-requiredCore math, datapath, scale, precision, or HW behavior needs review.Core math, datapath, scale, precision, or HW behavior needs review.priority:P1Next milestone blockerNext milestone blockertype:testbenchRequires simulation testbench, xsim runner, or golden comparison.Requires simulation testbench, xsim runner, or golden comparison.Status: Open.[P1][GEMV] Verify GEMV reduction pipeline and SFU/L2 output mux
area:gemvGEMV reduction, lane mask, activation broadcast, or output path.GEMV reduction, lane mask, activation broadcast, or output path.human-review-requiredCore math, datapath, scale, precision, or HW behavior needs review.Core math, datapath, scale, precision, or HW behavior needs review.priority:P1Next milestone blockerNext milestone blockertype:testbenchRequires simulation testbench, xsim runner, or golden comparison.Requires simulation testbench, xsim runner, or golden comparison.Status: Open.[P1][NPU_TOP] Connect result packer ready/valid and STORE writeback path
agent-safeSafe for AI agent: wiring, tests, scripts, docs, or scaffolding.Safe for AI agent: wiring, tests, scripts, docs, or scaffolding.area:npu-topTop-level NPU wiring, status, memory routing, or E2E path.Top-level NPU wiring, status, memory routing, or E2E path.priority:P1Next milestone blockerNext milestone blockertype:integrationConnects multiple modules or end-to-end system behavior.Connects multiple modules or end-to-end system behavior.type:rtlRequires RTL implementation or SystemVerilog module changes.Requires RTL implementation or SystemVerilog module changes.Status: Open.[P1][DISPATCHER] Redesign ctrl_npu_dispatcher for decoupled uop FIFOs
area:dispatcherInstruction decode, uop dispatch, FIFO, or async completion.Instruction decode, uop dispatch, FIFO, or async completion.human-review-requiredCore math, datapath, scale, precision, or HW behavior needs review.Core math, datapath, scale, precision, or HW behavior needs review.priority:P1Next milestone blockerNext milestone blockertype:designRequires design decision or spec clarification before implementation.Requires design decision or spec clarification before implementation.type:rtlRequires RTL implementation or SystemVerilog module changes.Requires RTL implementation or SystemVerilog module changes.Status: Open.[P0][NPU_TOP] Add minimal NPU_top end-to-end integration TB
agent-safeSafe for AI agent: wiring, tests, scripts, docs, or scaffolding.Safe for AI agent: wiring, tests, scripts, docs, or scaffolding.area:npu-topTop-level NPU wiring, status, memory routing, or E2E path.Top-level NPU wiring, status, memory routing, or E2E path.area:verificationSimulation, testbench, golden model, or xsim verification.Simulation, testbench, golden model, or xsim verification.priority:P0Drop-everythingDrop-everythingtype:integrationConnects multiple modules or end-to-end system behavior.Connects multiple modules or end-to-end system behavior.Status: Open.[P0][GEMV] Remove GEMV lane activation hardcode and connect lane mask
agent-safeSafe for AI agent: wiring, tests, scripts, docs, or scaffolding.Safe for AI agent: wiring, tests, scripts, docs, or scaffolding.area:gemvGEMV reduction, lane mask, activation broadcast, or output path.GEMV reduction, lane mask, activation broadcast, or output path.area:npu-topTop-level NPU wiring, status, memory routing, or E2E path.Top-level NPU wiring, status, memory routing, or E2E path.priority:P0Drop-everythingDrop-everythingtype:rtlRequires RTL implementation or SystemVerilog module changes.Requires RTL implementation or SystemVerilog module changes.Status: Open.[P0][GEMM] Validate DSP packer and sign recovery
area:gemmGEMM systolic array, DSP W4A8 MAC, packing, or recovery.GEMM systolic array, DSP W4A8 MAC, packing, or recovery.human-review-requiredCore math, datapath, scale, precision, or HW behavior needs review.Core math, datapath, scale, precision, or HW behavior needs review.priority:P0Drop-everythingDrop-everythingtype:testbenchRequires simulation testbench, xsim runner, or golden comparison.Requires simulation testbench, xsim runner, or golden comparison.Status: Open.