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    11 repositories

    • X6

      Public
      🚀 JavaScript diagramming library that uses SVG and HTML for rendering.
      TypeScript
      •
      MIT License
      •1.7k•0•0•0•Updated Jan 26, 2025Jan 26, 2025

    • inoculator-user-guide

      Public
      JavaScript
      •0•0•0•0•Updated Jan 22, 2025Jan 22, 2025

    • ramulator2

      Public
      Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
      C++
      •
      MIT License
      •64•0•0•0•Updated Jul 10, 2024Jul 10, 2024

    • amba-tlm

      Public
      AMBA TLM Library
      armtlmsystemcchiambaaxi4
      C++
      •0•4•0•0•Updated May 16, 2024May 16, 2024

    • antlr4_system_verilog_parser

      Public
      ANTLR4 grammar and parsing utilities for System Verilog 2017 (full support)
      SystemVerilog
      •
      MIT License
      •1•0•0•0•Updated Nov 11, 2023Nov 11, 2023

    • ramulator

      Public
      A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
      C++
      •
      MIT License
      •212•0•0•0•Updated Aug 29, 2023Aug 29, 2023

    • LAP

      Public
      Lark based DEF file parser
      Python
      •1•0•0•0•Updated Jun 4, 2023Jun 4, 2023

    • SD_AXIS_traffic_generator

      Public
      Software defined cycle accurate AXI Stream traffic generator
      Tcl
      •
      MIT License
      •1•1•0•0•Updated Dec 14, 2020Dec 14, 2020

    • logic

      Public
      CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
      SystemVerilog
      •
      Apache License 2.0
      •59•0•0•0•Updated Nov 25, 2019Nov 25, 2019

    • cycle-accurate-SystemC-simulator-over-ramulator

      Public
      An example of using Ramulator as memory model in a cycle-accurate SystemC Design
      C++
      •
      MIT License
      •9•0•0•0•Updated Jun 30, 2017Jun 30, 2017

    • DEF-Parser

      Public
      Design Exchange Format (DEF) parser toolkit copy. Cadence open-source parsers for DEF
      C++
      •
      Other
      •8•0•0•0•Updated Mar 30, 2016Mar 30, 2016