Board definition for CH32X033F8P6 TSSOP20

boards.txt

@@ -251,6 +251,23 @@ CH32X035_EVT.menu.pnum.CH32X035G8U.build.IQ_math_RV32=
 CH32X035_EVT.menu.pnum.CH32X035G8U.build.ch_extra_lib=-lprintf
 
 
+#CH32X033F8P EVT Board
+CH32X035_EVT.menu.pnum.CH32X033F8P=CH32X033F8P EVT
+CH32X035_EVT.menu.pnum.CH32X033F8P.node=NODE_X033F8P
+CH32X035_EVT.menu.pnum.CH32X033F8P.upload.maximum_size=63488
+CH32X035_EVT.menu.pnum.CH32X033F8P.upload.maximum_data_size=20480
+CH32X035_EVT.menu.pnum.CH32X033F8P.build.mcu=QingKe-V4C
+CH32X035_EVT.menu.pnum.CH32X033F8P.build.board=CH32X033F8P
+CH32X035_EVT.menu.pnum.CH32X033F8P.build.series=CH32X035
+CH32X035_EVT.menu.pnum.CH32X033F8P.build.variant=CH32X035/CH32X033F8P
+CH32X035_EVT.menu.pnum.CH32X033F8P.build.chip=CH32X033F8P
+CH32X035_EVT.menu.pnum.CH32X033F8P.build.march=rv32imacxw
+CH32X035_EVT.menu.pnum.CH32X033F8P.build.mabi=ilp32
+CH32X035_EVT.menu.pnum.CH32X033F8P.build.math_lib_gcc=-lm
+CH32X035_EVT.menu.pnum.CH32X033F8P.build.IQ_math_RV32=
+CH32X035_EVT.menu.pnum.CH32X033F8P.build.ch_extra_lib=-lprintf
+
+
 # Upload menu
 CH32X035_EVT.menu.upload_method.swdMethod=WCH-SWD
 CH32X035_EVT.menu.upload_method.swdMethod.upload.protocol=

variants/CH32X035/CH32X033F8P/CMakeLists.txt

@@ -0,0 +1,30 @@
+# v3.21 implemented semantic changes regarding $<TARGET_OBJECTS:...>
+# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
+cmake_minimum_required(VERSION 3.21)
+
+add_library(variant INTERFACE)
+add_library(variant_usage INTERFACE)
+
+target_include_directories(variant_usage INTERFACE
+  .
+)
+
+
+target_link_libraries(variant_usage INTERFACE
+  base_config
+)
+
+target_link_libraries(variant INTERFACE variant_usage)
+
+
+
+add_library(variant_bin STATIC EXCLUDE_FROM_ALL
+  PeripheralPins.c
+  variant_CH32X033F8P.cpp
+)
+target_link_libraries(variant_bin PUBLIC variant_usage)
+
+target_link_libraries(variant INTERFACE
+  variant_bin
+)
+

variants/CH32X035/CH32X033F8P/PeripheralPins.c

@@ -0,0 +1,206 @@
+/**
+ *******************************************************************************
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * This software component is licensed by WCH under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+#include "Arduino.h"
+#include "PeripheralPins.h"
+
+/* =====
+ * Notes:
+ * - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+ *   HW peripheral instances. You can use them the same way as any other "normal"
+ *   pin (i.e. analogWrite(PA7_ALT1, 128);).
+ *
+ * - Commented lines are alternative possibilities which are not used per default.
+ *   If you change them, you will have to know what you do
+ * =====
+ */
+
+//*** ADC ***
+#ifdef ADC_MODULE_ENABLED
+WEAK const PinMap PinMap_ADC[] = {
+  {PA_0,      ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 0)}, // ADC1_IN0
+  {PA_1,      ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 1)}, // ADC1_IN1
+  {PA_2,      ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 2)}, // ADC1_IN2
+  {PA_3,      ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 3)}, // ADC1_IN3
+  {PA_4,      ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 4)}, // ADC1_IN4
+  {PA_5,      ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 5)}, // ADC1_IN5
+  {PA_6,      ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 6)}, // ADC1_IN6
+//  {PA_7,      ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 7)}, // ADC1_IN7
+  {PB_0,      ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 8)}, // ADC1_IN8
+  {PB_1,      ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 9)}, // ADC1_IN9
+//  {PC_0,      ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 10)}, // ADC1_IN8
+  {PC_3,      ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 13)}, // ADC1_IN9
+  {NC,        NP,   0}
+};
+#endif
+
+//*** No DAC ***
+
+
+
+//*** I2C ***
+#ifdef I2C_MODULE_ENABLED
+WEAK const PinMap PinMap_I2C_SDA[] = {
+  {PC_17, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_PartialRemap2_I2C1_ENABLE)},
+  {PC_18, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_PartialRemap3_I2C1_ENABLE)},
+  {PC_16, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_PartialRemap4_I2C1_ENABLE)},
+  {PC_19, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_FullRemap_I2C1_ENABLE)},  
+  {NC,   NP,   0}
+};
+#endif
+
+#ifdef I2C_MODULE_ENABLED
+WEAK const PinMap PinMap_I2C_SCL[] = {
+  {PC_16, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_PartialRemap2_I2C1_ENABLE)},
+  {PC_19, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_PartialRemap3_I2C1_ENABLE)},
+  {PC_17, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_PartialRemap4_I2C1_ENABLE)},  
+  {PC_18, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_FullRemap_I2C1_ENABLE)},  
+  {NC,   NP,   0}
+};
+#endif
+
+//*** TIM ***
+#ifdef TIM_MODULE_ENABLED
+WEAK const PinMap PinMap_TIM[] = {
+
+//  {PB_9,       TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_PartialRemap1_TIM1_ENABLE, 1)}, // TIM1_CH1_1
+//  {PB_10,      TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_PartialRemap1_TIM1_ENABLE, 2)}, // TIM1_CH2_1
+//  {PB_11,      TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_PartialRemap1_TIM1_ENABLE, 3)}, // TIM1_CH3_1
+//  {PC_16,      TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_PartialRemap1_TIM1_ENABLE, 4)}, // TIM1_CH4_1
+//  {PA_7,       TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_PartialRemap1_TIM1_ENABLE, 1)}, // TIM1_CH1N_1
+//  {PB_0,       TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_PartialRemap1_TIM1_ENABLE, 2)}, // TIM1_CH2N_1
+//  {PB_1,       TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_PartialRemap1_TIM1_ENABLE, 3)}, // TIM1_CH3N_1
+  {PB_1,       TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_PartialRemap1_TIM1_ENABLE, 3)}, // TIM1_CH3N_1  (MMOLE 241012 NOK)
+//  {PC_3,       TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_PartialRemap2_TIM2_ENABLE, 1)}, // TIM2_CH1N_2  (MMOLE 241012 NOK)
+  {PC_3,       TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_PartialRemap3_TIM1_ENABLE, 4)}, // TIM1_CH4_3  (MMOLE 241012 OK)
+
+//  {PC_19,      TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_FullRemap_TIM2_ENABLE, 1)}, // TIM2_CH1_6
+//  {PC_14,      TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_FullRemap_TIM2_ENABLE, 2)}, // TIM2_CH2_6
+//  {PC_15,      TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_FullRemap_TIM2_ENABLE, 3)}, // TIM2_CH3_6
+//  {PC_0,       TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_FullRemap_TIM2_ENABLE, 4)}, // TIM2_CH4_6
+//  {PB_11,      TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_FullRemap_TIM2_ENABLE, 1)}, // TIM2_CH1N_6
+//  {PB_12,      TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_FullRemap_TIM2_ENABLE, 2)}, // TIM2_CH2N_6
+//  {PB_3,       TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_FullRemap_TIM2_ENABLE, 3)}, // TIM2_CH3N_6
+//  {PC_3,       TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_FullRemap_TIM2_ENABLE, 3)}, // TIM2_CH1N_6
+  {PA_4,       TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_FullRemap_TIM3_ENABLE, 2)}, // TIM3_CH2_3  (MMOLE 241012 OK)
+
+//  {PA_6,       TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_NONE, 1)}, // TIM2_CH2N_6
+//  {PA_7,       TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_NONE, 2)}, // TIM3_CH2 PA7 cannot be output on CH32X033F8P6
+  {PA_0,       TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_NONE, 1)}, // TIM2_CH1  (MMOLE 241012 OK)
+  {PA_1,       TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_NONE, 2)}, // TIM2_CH2  (MMOLE 241012 OK)
+  {PA_2,       TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_NONE, 3)}, // TIM2_CH3  (MMOLE 241012 OK)
+  {PA_3,       TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_NONE, 4)}, // TIM2_CH4  (MMOLE 241012 OK)
+  {PA_6,       TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_NONE, 1)}, // TIM3_CH1  (MMOLE 241012 OK)
+  {PB_7,       TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_NONE, 2)}, // TIM1_CH2N (MMOLE 241012 NOK)
+
+  {NC,         NP,   0}
+};
+#endif
+
+// TODO: adjust UART pins to CH32X033F8P6: PA2/PA3 + USB?
+//*** UART ***
+#ifdef UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_TX[] = {
+  {PA_10, USART1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_PartialRemap1_USART1_ENABLE)},    // was PB_10 AFIO_NONE, now: alternative PA10 for TX1_1
+  {PA_2,  USART2, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},    // was PA_2
+  {PB_3,  USART3, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
+  {PB_0,  USART4, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
+  {NC,   NP,     0}
+};
+#endif
+
+#ifdef UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_RX[] = {
+  {PA_11, USART1, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_PartialRemap1_USART1_ENABLE)},    // was PB_11 AFIO_NONE, now: alternative PA11 for RX1_1
+  {PA_3,  USART2, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},    // was PA_3
+  {PB_4,  USART3, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
+  {PB_1,  USART4, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
+  {NC,    NP,     0}
+};
+#endif
+
+#ifdef UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_RTS[] = {
+  {PC_17, USART1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},    // was PC_17
+  {PA_1,  USART2, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},    // was PA_1
+  {PB_7,  USART3, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
+  {PA_8,  USART4, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
+  {NC,    NP,     0}
+};
+#endif
+
+#ifdef UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_CTS[] = {
+  {PC_16, USART1, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},    // was PC_16  
+  {PA_0,  USART2, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},    // was PA_0  
+  {PB_6,  USART3, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},  
+  {PB_15, USART4, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},  
+  {NC,    NP,     0}
+};
+#endif
+
+
+//*** SPI ***
+#ifdef SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_MOSI[] = {
+  {PA_7, SPI1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
+  {NC,   NP,   0}
+};
+#endif
+
+#ifdef SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_MISO[] = {
+  {PA_6, SPI1, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_FLOAT, 0, AFIO_NONE)},
+  {NC,   NP,   0}
+};
+#endif
+
+#ifdef SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_SCLK[] = {
+  {PA_5, SPI1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
+  {NC,   NP,   0}
+};
+#endif
+
+#ifdef SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_SSEL[] = {
+  {PA_4,  SPI1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
+  {NC,    NP,   0}
+};
+#endif
+
+//*** NO CAN ***
+#ifdef CAN_MODULE_ENABLED
+
+#endif
+
+#ifdef CAN_MODULE_ENABLED 
+
+#endif
+
+//*** No ETHERNET ***
+
+
+
+//*** USB ***
+#ifdef USB_MODULE_ENABLED
+WEAK const PinMap PinMap_USB[] = {
+  {PC_16, USB, CH_PIN_DATA(CH_MODE_INPUT, GPIO_NOPULL, AFIO_NONE)}, // USB_DM
+  {PC_17, USB, CH_PIN_DATA(CH_MODE_INPUT, GPIO_NOPULL, AFIO_NONE)}, // USB_DP
+  {NC,    NP,  0}
+};
+#endif
+
+//*** No SD ***
+
+

variants/CH32X035/CH32X033F8P/PinNamesVar.h

@@ -0,0 +1,11 @@
+/* Alternate pin name */
+
+/* SYS_WKUP */
+#ifdef PWR_WAKEUP_PIN1
+  SYS_WKUP1 = PA_0,
+#endif
+/* USB */
+#ifdef USBCON
+  USB_DM = PC_16,
+  USB_DP = PC_17,
+#endif

variants/CH32X035/CH32X033F8P/README.md

@@ -0,0 +1,49 @@
+## CH32X033F8P6 ##
+
+### CH32X035/X033 Main Features ###
+-	48MHz RC oscillator
+-	20KB SRAM
+-	62KB Flash + 3328B System Flash
+-	256B system config + 256B user storage
+-	2x OPA, 3x CMP, 12-bit 14-chn ADC, 14-chn touch
+-	3x 16-bit timer, 2x WD timer, systick
+-	4x USART, I2C, SPI, USB2, USB PD, 2-wire debug
+
+
+### TSSOP20 Pinout ###
+- See [datasheet](https://www.wch.cn/downloads/CH32X035DS0_PDF.html) for complete pin function list.
+```
+                  +------v------+
+    MISO/A6 D6~ 1-+PA6       PA5+-20  D5 SCK/A5
+MOSI/A8/TX4 D7  2-+PA7=PB0   PA4+-19  D4~ CS/A4
+     A9/RX4 D8  3-+PB1      PC19+-18  D17 SWCLK
+       /RST D9  4-+PB7       PA3+-17  D3~ RX2/A3*
+     USBDM D10  5-+PC16=PC11 PA2+-16  D2~ TX2/A2
+     USBDP D11  6-+PC17=PC10 PA1+-15  D1~ A1
+           GND  7-+VSS       PA0+-14  D0~ A0
+     SWDIO D16  8-+PC18      PC3+-13  D15~ A13
+           VCC  9-+VDD      PA10+-12  D14/SCL
+           D12 10-+PA9      PA11+-11  D13/SDA
+                  +-------------+
+*A3 and I2C don't work on CH32X033F8P6 0-series (lot number with the penultimate bit 5 being 0).
+```
+
+
+### Tested features ###
+- digitalWrite()/digitalRead() - can use Arduino pin numbers or PAx notation.
+- analogWrite() - 12-bit resolution, pins marked with ~ in pinout above.
+- analogRead() - very stable 12-bit resolution, but issues with A3/A0/PADC_VREF
+- Serial.print() - Tested 115200 bps on PA2/PA3 (as set in variant_CH32X033F8P6.h)
+- EEPROM library - may need improvement (first test showed corrupted data written).
+- Pin PB7 (Arduino pin 9) can be configured as hardware reset /RST using WCH Link Utility. (See issue #123)
+
+### Known issues/limitations ###
+- Pins PA7/PB0, PC16/PC11 and PC17/PC10 cannot be used for output.
+- Any signal on A0 seems to show on other ADC pins when disconnected.
+- A3, PADC_VREF and I2C don't work on CH32X033F8P6 0-series (lot number with the penultimate bit 5 being 0).
+
+### References ###
+- [datasheet](https://www.wch.cn/downloads/CH32X035DS0_PDF.html)
+- [reference manual](https://www.wch.cn/downloads/CH32X035RM_PDF.html)
+- [X033/X035 ](https://github.com/openwch/ch32x035), [WCH examples](https://github.com/openwch/ch32x035/blob/main/EVT/EXAM)
+- [PIOC](https://github.com/openwch/ch32x035/tree/main/EVT/EXAM/PIOC) [User manual](https://github.com/openwch/ch32x035/blob/main/EVT/EXAM/PIOC/PIOC%20UserManual.pdf), [Reference manual](https://github.com/openwch/ch32x035/blob/main/EVT/EXAM/PIOC/PIOC-EN.pdf), [Instruction set](https://github.com/openwch/ch32x035/blob/main/EVT/EXAM/PIOC/CHRISC8B-EN.pdf)

variants/CH32X035/CH32X033F8P/boards_entry.txt

@@ -0,0 +1,12 @@
+# This file help to add generic board entry.
+
+
+
+# CH32X033F8P
+CH32X035_EVT.menu.pnum.CH32X033F8P=CH32X033F8P EVT
+CH32X035_EVT.menu.pnum.CH32X033F8P.upload.maximum_size=63488
+CH32X035_EVT.menu.pnum.CH32X033F8P.upload.maximum_data_size=20480
+CH32X035_EVT.menu.pnum.CH32X033F8P.build.board=CH32X033F8P
+CH32X035_EVT.menu.pnum.CH32X033F8P.build.product_line=CH32X035
+CH32X035_EVT.menu.pnum.CH32X033F8P.build.variant=CH32X035/CH32X033F8P
+

variants/CH32X035/CH32X033F8P/variant_CH32X033F8P.cpp

@@ -0,0 +1,60 @@
+/**
+ *******************************************************************************
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * This software component is licensed by WCH under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+#include "pins_arduino.h"
+
+
+
+
+// Digital PinName array
+const PinName digitalPin[] = {
+  PA_0,   // D0  A0
+  PA_1,   // D1  A1
+  PA_2,   // D2  TX2/A2
+  PA_3,   // D3  RX2/A3
+  PA_4,   // D4  CS/A4
+  PA_5,   // D5  SCK/A5
+  PA_6,   // D6  MISO/A6
+  PB_0,   // D7  MOSI/A8  PA7 is tied to PB0 => input only 
+  PB_1,   // D8  A9
+  PB_7,   // D9  RST
+  PC_16,  // D10 USBDM  tied to PC11=input only 
+  PC_17,  // D11 USBPD  tied to PC10=input only 
+  PA_9,   // D12
+  PA_11,  // D13 SDA (not in 0-series)
+  PA_10,  // D14 SCL (not in 0-series)
+  PC_3,   // D15 A13
+  PC_18,  // D16 SWDIO
+  PC_19,  // D17 SWCLK
+};
+
+// Analog (Ax) pin number array, refers to PinName in digitalPin[]?
+const uint32_t analogInputPin[] = {
+  0,  // A0,  PA0 
+  1,  // A1,  PA1
+  2,  // A2,  PA2
+  3,  // A3,  PA3 (no ADC Ch3 in 0-series!)
+  4,  // A4,  PA4
+  5,  // A5,  PA5
+  6,  // A6,  PA6
+  7,  // A7,  PA7=PB0, input only
+  7,  // A8,  PB0=PA7, input only
+  8,  // A9,  PB1
+  10, // A10, none
+  11, // A11, none
+  12, // A12, none
+  15, // A13, PC3
+};
+
+
+