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Address space of an SoC using A2I core

Status: Open.

#52 In openpower-cores/a2i;

· Grubby-CPU opened on Jun 29, 2022

About some unknow instructions in A2 Core

core RTL/Architecture

documentationImprovements or additions to documentationImprovements or additions to documentation

Status: Open.

#51 In openpower-cores/a2i;

· Grubby-CPU opened on Jun 8, 2022

Why msgclr does not set UsesSPR in iuq_fxu_decode.vhdl

Status: Open.

#50 In openpower-cores/a2i;

· Grubby-CPU opened on Apr 14, 2022

About the memory consistency model in A2

Status: Open.

#49 In openpower-cores/a2i;

· Grubby-CPU opened on Apr 10, 2022

Error happens when two threads co-execute together

core RTL/Architecture

Status: Open.

#47 In openpower-cores/a2i;

· Grubby-CPU opened on Feb 28, 2022

Why choosing ex4 to deal with interrupt and exception

core RTL/Architecture

Status: Open.

#44 In openpower-cores/a2i;

· Grubby-CPU opened on Oct 12, 2021

How to deal with wrong target address prediction of link stack

core RTL/Architecture

Status: Open.

#41 In openpower-cores/a2i;

· Grubby-CPU opened on May 13, 2021

A design drawback of thread issue selection?

core RTL/Architecture

Status: Open.

#37 In openpower-cores/a2i;

· zhaoxiahust opened on Nov 12, 2020

Any hints about the ignore_flush_is0 signal

core RTL/Architecture

Status: Open.

#33 In openpower-cores/a2i;

· zhaoxiahust opened on Oct 29, 2020

Problem in simulation of the a2l2_axi.vhdl file

core RTL/Architecture

Status: Open.

#32 In openpower-cores/a2i;

· xinyu8888 opened on Oct 28, 2020

The RAW/WAW dependency check in iuq_fxu_dep.vhdl

core RTL/Architecture

Status: Open.

#29 In openpower-cores/a2i;

· Grubby-CPU opened on Sep 10, 2020

Questions about the medium priority when selecting threads to issue

core RTL/Architecture

Status: Open.

#22 In openpower-cores/a2i;

· Jackhuang-code opened on Sep 2, 2020