Nv large vp

README.md

@@ -12,8 +12,9 @@ You can find the latest NVDLA Virtual Platform documentation for AWS FPGA [here]
 
 ## NVIDIA Sample AFI
 
-agfi-0373fee35268723ca
+nv_small: agfi-0373fee35268723ca
+nv_large: agfi-0f541fc533cba53ef
 
 ## EC2 FPGA Hardware and Software Development Kits version
 
-be3d41cb1b6b5db6bc24b577ab1af8d2eb4de102
+v1.4.0

cl_nvdla/build/constraints/cl_pnr_user.xdc

@@ -1,26 +1,10 @@
 # This contains the CL specific constraints for Top level PNR
 
-create_pblock pblock_CL_top
-resize_pblock [get_pblocks pblock_CL_top] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14}
-set_property PARENT pblock_CL [get_pblocks pblock_CL_top]
+# False path between vled on CL clock and Shell asynchronous clock
+set_false_path -from [get_cells WRAPPER_INST/CL/vled_q_reg*] 
 
-create_pblock pblock_CL_mid
-add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells -quiet -hierarchical -filter {NAME =~ CL/CL_DMA_PCIS_SLV/AXI_CROSSBAR}]
-add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells -quiet -hierarchical -filter {NAME =~ CL/CL_PCIM_MSTR/CL_TST_PCI}] -clear_locs
-add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells [list CL/CL_PCIM_MSTR/PCI_AXI4_REG_SLC]]
-resize_pblock [get_pblocks pblock_CL_mid] -add {CLOCKREGION_X0Y5:CLOCKREGION_X3Y9}
-set_property PARENT pblock_CL [get_pblocks pblock_CL_mid]
-
-create_pblock pblock_CL_bot
-add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells [list CL/CL_DMA_PCIS_SLV/PCI_AXL_REG_SLC CL/CL_OCL_SLV/AXIL_OCL_REG_SLC CL/CL_SDA_SLV/AXIL_SDA_REG_SLC]]
-add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -hierarchical -filter { NAME =~  "*CL/CL_OCL_SLV/slv_tst_wdata_reg[*][*]*" && PRIMITIVE_TYPE =~ REGISTER.*.* }]
-#Reassign select cells to parent Pblock for better QoR
-add_cells_to_pblock [get_pblocks pblock_CL] $pblock_cells
-resize_pblock [get_pblocks pblock_CL_bot] -add {CLOCKREGION_X0Y0:CLOCKREGION_X3Y4}
-set_property PARENT pblock_CL [get_pblocks pblock_CL_bot]
-
-set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
+# False paths between main clock and tck
+set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins WRAPPER_INST/SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
 set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
 set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
 
-

cl_nvdla/build/scripts/README.md

@@ -6,8 +6,10 @@
     > git clone https://github.com/aws/aws-fpga.git 
 3.  Souce aws-fpga hdk environment:
     > source aws-fpga/hdk_setup.sh
-4.  generate nvdla file list:
-    > ./filelist.sh
-4.  Command line to build nvdla in aws fpga: 
+4.  Generate nvdla file list:
+    > ./filelist.sh [nv_large | nv_medium_1024_full | nv_medium_512 | nv_small_256_full | nv_small_256 | nv_small]
+5.  Change the verilog define in file synth_cl_nvdla.tcl for different configure 
+    > -verilog_define NV_LARGE | NV_MEDIUM_1024_FULL | NV_MEDIUM_512 |  NV_SMALL_256_FULL |  NV_SMALL_256 |  NV_SMALL
+6.  Command line to build nvdla in aws fpga: 
     > $HDK_DIR/common/shell_stable/build/scripts/aws_build_dcp_from_cl.sh -foreground -clock_recipe_a A2
 

cl_nvdla/build/scripts/create_dcp_from_cl.tcl

@@ -13,16 +13,13 @@
 # implied. See the License for the specific language governing permissions and
 # limitations under the License.
 
-# Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
-# NVIDIA’s contributions are offered under the Amazon Software License
-
 package require tar
 
 ## Do not edit $TOP
 set TOP top_sp
 
 ## Replace with the name of your module
-set CL_MODULE cl_nvdla  
+set CL_MODULE cl_nvdla
 
 #################################################
 ## Command-line Arguments
@@ -113,37 +110,28 @@ set_msg_config -string {AXI_QUAD_SPI} -suppress
 # may comment them out if they wish to see more information from warning
 # messages.
 set_msg_config -id {Common 17-55}        -suppress
-set_msg_config -id {Designutils 20-1567} -suppress
+set_msg_config -id {Vivado 12-4739}      -suppress
+set_msg_config -id {Constraints 18-4866} -suppress
 set_msg_config -id {IP_Flow 19-2162}     -suppress
-set_msg_config -id {Project 1-498}       -suppress
 set_msg_config -id {Route 35-328}        -suppress
+set_msg_config -id {Vivado 12-1008}      -suppress
 set_msg_config -id {Vivado 12-508}       -suppress
-set_msg_config -id {Constraints 18-4866} -suppress
 set_msg_config -id {filemgmt 56-12}      -suppress
-set_msg_config -id {Constraints 18-4644} -suppress
-set_msg_config -id {Coretcl 2-64}        -suppress
-set_msg_config -id {Vivado 12-4739}      -suppress
-set_msg_config -id {Vivado 12-5201}      -suppress
 set_msg_config -id {DRC CKLD-1}          -suppress
+set_msg_config -id {DRC CKLD-2}          -suppress
 set_msg_config -id {IP_Flow 19-2248}     -suppress
-set_msg_config -id {Opt 31-155}          -suppress
-set_msg_config -id {Synth 8-115}         -suppress
-set_msg_config -id {Synth 8-3936}        -suppress
-set_msg_config -id {Vivado 12-1023}      -suppress
+set_msg_config -id {Vivado 12-1580}      -suppress
 set_msg_config -id {Constraints 18-550}  -suppress
 set_msg_config -id {Synth 8-3295}        -suppress
 set_msg_config -id {Synth 8-3321}        -suppress
 set_msg_config -id {Synth 8-3331}        -suppress
 set_msg_config -id {Synth 8-3332}        -suppress
+set_msg_config -id {Synth 8-6014}        -suppress
+set_msg_config -id {Timing 38-436}       -suppress
+set_msg_config -id {DRC REQP-1853}       -suppress
 set_msg_config -id {Synth 8-350}         -suppress
 set_msg_config -id {Synth 8-3848}        -suppress
 set_msg_config -id {Synth 8-3917}        -suppress
-set_msg_config -id {Synth 8-6014}        -suppress
-set_msg_config -id {Vivado 12-1580}      -suppress
-set_msg_config -id {Constraints 18-619}  -suppress
-set_msg_config -id {DRC CKLD-2}          -suppress
-set_msg_config -id {DRC REQP-1853}       -suppress
-set_msg_config -id {Timing 38-436}       -suppress
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl.";
 
@@ -204,12 +192,16 @@ source $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
 
 source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl
-
+#################################################################
+#### Do not remove this setting. Need to workaround bug in 2017.4
+#################################################################
+set_param hd.clockRoutingWireReduction false
 ##################################################
 ### CL XPR OOC Synthesis
 ##################################################
 if {${cl.synth}} {
    source -notrace ./synth_${CL_MODULE}.tcl
+   set synth_dcp ${timestamp}.CL.post_synth.dcp
 }
 
 ##################################################
@@ -227,7 +219,7 @@ if {$implement} {
       puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Combining Shell and CL design checkpoints";
       add_files $HDK_SHELL_DIR/build/checkpoints/from_aws/SH_CL_BB_routed.dcp
       add_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp
-      set_property SCOPED_TO_CELLS {CL} [get_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp]
+      set_property SCOPED_TO_CELLS {WRAPPER_INST/CL} [get_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp]
 
       #Read the constraints, note *DO NOT* read cl_clocks_aws (clocks originating from AWS shell)
       read_xdc [ list \
@@ -236,7 +228,7 @@ if {$implement} {
       set_property PROCESSING_ORDER late [get_files cl_pnr_user.xdc]
 
       puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running link_design";
-      link_design -top $TOP -part [DEVICE_TYPE] -reconfig_partitions {SH CL}
+      link_design -top $TOP -part [DEVICE_TYPE] -reconfig_partitions {WRAPPER_INST/SH WRAPPER_INST/CL}
 
       puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - PLATFORM.IMPL==[get_property PLATFORM.IMPL [current_design]]";
       ##################################################
@@ -309,7 +301,11 @@ if {$implement} {
    # This is what will deliver to AWS
    puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Writing final DCP to to_aws directory.";
 
-   write_checkpoint -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp
+   #writing unencrypted dcp for analysis to checkpoints dir.
+   write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.SH_CL_routed.dcp
+
+   #writing encrypted dcp which can be sent to AWS
+   write_checkpoint -encrypt -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp
 
    # Generate debug probes file
    write_debug_probes -force -no_partial_ltxfile -file $CL_DIR/build/checkpoints/${timestamp}.debug_probes.ltx
@@ -328,8 +324,18 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Compress files for
 # Create manifest file
 set manifest_file [open "$CL_DIR/build/checkpoints/to_aws/${timestamp}.manifest.txt" w]
 set hash [lindex [split [exec sha256sum $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp] ] 0]
-
+set TOOL_VERSION $::env(VIVADO_TOOL_VERSION)
+set vivado_version [version -short]
+set ver_2017_4 2017.4
+puts "vivado_version is $vivado_version\n"
+
+if { [string first  $ver_2017_4 $vivado_version] == 0 } {
+puts $manifest_file "manifest_format_version=2\n"
+puts "in 2017.4"
+} else {
 puts $manifest_file "manifest_format_version=1\n"
+puts "in 2017.1"
+}
 puts $manifest_file "pci_vendor_id=$vendor_id\n"
 puts $manifest_file "pci_device_id=$device_id\n"
 puts $manifest_file "pci_subsystem_id=$subsystem_id\n"
@@ -338,6 +344,9 @@ puts $manifest_file "dcp_hash=$hash\n"
 puts $manifest_file "shell_version=$shell_version\n"
 puts $manifest_file "dcp_file_name=${timestamp}.SH_CL_routed.dcp\n"
 puts $manifest_file "hdk_version=$hdk_version\n"
+if { [string first $ver_2017_4 $vivado_version] == 0} {
+puts $manifest_file "tool_version=v2017.4\n"
+}
 puts $manifest_file "date=$timestamp\n"
 puts $manifest_file "clock_recipe_a=$clock_recipe_a\n"
 puts $manifest_file "clock_recipe_b=$clock_recipe_b\n"
@@ -359,7 +368,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Finished creating
 
 if {[string compare $notify_via_sns "1"] == 0} {
   puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Calling notification script to send e-mail to $env(EMAIL)";
-  exec $env(HDK_COMMON_DIR)/scripts/notify_via_sns.py
+  exec $env(AWS_FPGA_REPO_DIR)/shared/bin/scripts/notify_via_sns.py
 }
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Build complete.";

cl_nvdla/build/scripts/filelist.sh

@@ -7,6 +7,8 @@
 # ================================================================
 
 rm -rf ./nvdla_file.tcl
+rm -rf ../src_post_encryption
+version=$1
 
 SelecSource(){
 local_folder=$1
@@ -29,11 +31,11 @@ sed '/'$local_file'/d' nvdla_file.tcl > nvdla_file.tcl_temp
 mv nvdla_file.tcl_temp nvdla_file.tcl
 }
 
-ip_path=outdir/nv_small/spec/manual
+ip_path=outdir/$version/spec/manual
 file_type=v
 SelecSource $ip_path $file_type
 
-ip_path=outdir/nv_small/vmod/nvdla
+ip_path=outdir/$version/vmod/nvdla
 file_type=v
 folder_list=`ls ${NV_HW_ROOT}/${ip_path}`
 echo ${folder_list}
@@ -42,33 +44,49 @@ do
 SelecSource ${ip_path}/$folder $file_type
 done
 
-ip_path=outdir/nv_small/vmod/include
+ip_path=outdir/$version/vmod/include
 file_type=vh
 SelecSource ${ip_path} $file_type
 
-ip_path=outdir/nv_small/vmod/vlibs
+ip_path=outdir/$version/vmod/vlibs
 file_type=v
 SelecSource ${ip_path} $file_type
 
-ip_path=outdir/nv_small/spec/defs
+ip_path=outdir/$version/spec/defs
 file_type=vh
 SelecSource ${ip_path} $file_type
 
-export PATH=.:$PATH
-echo "dla_ramgen -m nv_ram_rwsp_8x65" >> ${NV_HW_ROOT}/vmod/rams/fpga/run_small_ram
-echo "dla_ramgen -m nv_ram_rws_256x64" >> ${NV_HW_ROOT}/vmod/rams/fpga/run_small_ram
-cur_path=`pwd`
-cd  ${NV_HW_ROOT}/vmod/rams/fpga
-./run_small_ram
-mkdir -p ${NV_HW_ROOT}/outdir/nv_small/vmod/rams/fpga/small_rams
-mv ${NV_HW_ROOT}/vmod/rams/fpga/*.v ${NV_HW_ROOT}/outdir/nv_small/vmod/rams/fpga/small_rams
-cd ${cur_path}
+#export PATH=.:$PATH
+#echo "dla_ramgen -m nv_ram_rwsp_8x65" >> ${NV_HW_ROOT}/vmod/rams/fpga/run_small_ram
+#echo "dla_ramgen -m nv_ram_rws_256x64" >> ${NV_HW_ROOT}/vmod/rams/fpga/run_small_ram
+#cur_path=`pwd`
+#cd  ${NV_HW_ROOT}/vmod/rams/fpga
+#./run_small_ram
+#mkdir -p ${NV_HW_ROOT}/outdir/$version/vmod/rams/fpga/small_rams
+#mv ${NV_HW_ROOT}/vmod/rams/fpga/*.v ${NV_HW_ROOT}/outdir/$version/vmod/rams/fpga/small_rams
+#cd ${cur_path}
 
-ip_path=outdir/nv_small/vmod/rams/fpga/small_rams
+ip_path=outdir/$version/vmod/rams/fpga/model
 file_type=v
 SelecSource ${ip_path} $file_type
 
+ip_path=outdir/$version/vmod/fifos
+file_type=v
+SelecSource ${ip_path} $file_type
+
+if [ $version == "nv_large" ]
+then
+file_remove_list="NV_NVDLA_CDP_DP_bufferin_tp1.v NV_NVDLA_CVIF_WRITE_IG_arb.v"
+elif [ $version == "nv_medium_1024_full" ]
+then
+file_remove_list="NV_NVDLA_CDP_DP_bufferin_tp1.v"
+elif [ $version == "nv_medium_512" ]
+then
 file_remove_list="NV_NVDLA_SDP_CORE_Y_lut.v NV_NVDLA_SDP_HLS_Y_cvt_top.v NV_NVDLA_SDP_HLS_Y_idx_top.v NV_NVDLA_SDP_HLS_Y_inp_top.v NV_NVDLA_SDP_HLS_Y_int_core.v"
+else 
+file_remove_list="NV_NVDLA_SDP_CORE_Y_lut.v NV_NVDLA_SDP_HLS_Y_cvt_top.v NV_NVDLA_SDP_HLS_Y_idx_top.v NV_NVDLA_SDP_HLS_Y_inp_top.v NV_NVDLA_SDP_HLS_Y_int_core.v"
+fi 
+
 for each_file in $file_remove_list
 do
 RemoveFile $each_file 

cl_nvdla/build/scripts/synth_cl_nvdla.tcl

@@ -98,6 +98,9 @@ read_bd [ list \
 #Read Xilinx interconnection IP
 read_ip [ list \
   $CL_DIR/../common/design/xilinx_ip/axi_interconnect_nvdla_64b/axi_interconnect_nvdla_64b.xci \
+  $CL_DIR/../common/design/xilinx_ip/axi_interconnect_nv_large/axi_interconnect_nv_large.xci \
+  $CL_DIR/../common/design/xilinx_ip/axi_interconnect_nvdla_128b/axi_interconnect_nvdla_128b.xci \
+  $CL_DIR/../common/design/xilinx_ip/axi_interconnect_nvdla_64b_cvsram/axi_interconnect_nvdla_64b_cvsram.xci \
   $CL_DIR/../common/design/xilinx_ip/axi_apb_bridge_0/axi_apb_bridge_0.xci 
 ]
 
@@ -128,8 +131,9 @@ set_property PROCESSING_ORDER EARLY  [get_files cl_clocks_aws.xdc]
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthesis.";
 
 update_compile_order -fileset sources_1
+#-verilog_define NV_LARGE | NV_MEDIUM_1024_FULL | NV_MEDIUM_512 |  NV_SMALL_256_FULL |  NV_SMALL_256 |  NV_SMALL
 puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
-eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -verilog_define  FPGA -verilog_define SYNTHESIS -verilog_define DESIGNWARE_NOEXIST -verilog_define VLIB_BYPASS_POWER_CG -verilog_define NV_FPGA_SYSTEM -verilog_define NV_FPGA_FIFOGEN  -verilog_define NV_FPGA_UNIT -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
+eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -verilog_define  FPGA -verilog_define SYNTHESIS -verilog_define DESIGNWARE_NOEXIST -verilog_define VLIB_BYPASS_POWER_CG -verilog_define NV_FPGA_SYSTEM -verilog_define NV_FPGA_FIFOGEN  -verilog_define NV_FPGA_UNIT -verilog_define NV_LARGE  -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
 
 set failval [catch {exec grep "FAIL" failfast.csv}]
 if { $failval==0 } {

cl_nvdla/design/cl_dma_pcis_slv.sv

@@ -16,6 +16,8 @@
 // Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved.
 // NVIDIA’s contributions are offered under the Amazon Software License
 
+`include "cl_nvdla_defines.vh"
+
 module cl_dma_pcis_slv #(parameter SCRB_MAX_ADDR = 64'h3FFFFFFFF, parameter SCRB_BURST_LEN_MINUS1 = 15, parameter NO_SCRB_INST = 1)
 
 (
@@ -126,10 +128,16 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in
 //---------------------------- 
 // axi interconnect for DDR address decodes 
 //---------------------------- 
-`ifdef NVDLA_CVSRAM_PRESENT
-(* dont_touch = "true" *) axi_interconnect_nvdla_512b AXI_INTERCONNECT ( 
-`else
-(* dont_touch = "true" *) axi_interconnect_nvdla_64b AXI_INTERCONNECT ( 
+`ifdef NVDLA_AXI_WIDTH_256
+	(* dont_touch = "true" *) axi_interconnect_nv_large  AXI_INTERCONNECT ( 
+`elsif NVDLA_AXI_WIDTH_128
+	(* dont_touch = "true" *) axi_interconnect_nvdla_128b AXI_INTERCONNECT ( 
+`else 
+	`ifdef NVDLA_CVSRAM_PRESENT
+		(* dont_touch = "true" *) axi_interconnect_nvdla_64b_cvsram AXI_INTERCONNECT ( 
+	`else
+		(* dont_touch = "true" *) axi_interconnect_nvdla_64b AXI_INTERCONNECT ( 
+	`endif
 `endif
      .INTERCONNECT_ACLK     (aclk)
     ,.INTERCONNECT_ARESETN  (slr1_sync_aresetn)

cl_nvdla/design/cl_nvdla.sv

@@ -69,8 +69,17 @@ axi_bus_t sh_cl_dma_pcis_bus();
 axi_bus_t sh_cl_dma_pcis_q();
 // keep below nvdla_axi_0/1 i/f same as nvdla configuration. Note: nvdla, axi_data_width=512,axi_len_width=4 
 `ifdef NVDLA_CVSRAM_PRESENT
-axi_bus_t #(.AWS_FPGA_AXI_BUS_DATA_WIDTH(512), .AWS_FPGA_AXI_BUS_ID_WIDTH(8), .AWS_FPGA_AXI_BUS_ADDR_WIDTH(64), .AWS_FPGA_AXI_BUS_LEN_WIDTH(4)) nvdla_dbb_axi_bus();
-axi_bus_t #(.AWS_FPGA_AXI_BUS_DATA_WIDTH(512), .AWS_FPGA_AXI_BUS_ID_WIDTH(8), .AWS_FPGA_AXI_BUS_ADDR_WIDTH(64), .AWS_FPGA_AXI_BUS_LEN_WIDTH(4)) nvdla_cvsram_axi_bus();
+`ifdef NVDLA_AXI_WIDTH_256
+axi_bus_t #(.AWS_FPGA_AXI_BUS_DATA_WIDTH(256), .AWS_FPGA_AXI_BUS_ID_WIDTH(8), .AWS_FPGA_AXI_BUS_ADDR_WIDTH(64), .AWS_FPGA_AXI_BUS_LEN_WIDTH(4)) nvdla_cvsram_axi_bus();
+`else
+axi_bus_t #(.AWS_FPGA_AXI_BUS_DATA_WIDTH(64), .AWS_FPGA_AXI_BUS_ID_WIDTH(8), .AWS_FPGA_AXI_BUS_ADDR_WIDTH(64), .AWS_FPGA_AXI_BUS_LEN_WIDTH(4)) nvdla_cvsram_axi_bus();
+`endif
+`endif
+
+`ifdef NVDLA_AXI_WIDTH_256
+axi_bus_t #(.AWS_FPGA_AXI_BUS_DATA_WIDTH(256), .AWS_FPGA_AXI_BUS_ID_WIDTH(8), .AWS_FPGA_AXI_BUS_ADDR_WIDTH(64), .AWS_FPGA_AXI_BUS_LEN_WIDTH(4)) nvdla_dbb_axi_bus();
+`elsif NVDLA_AXI_WIDTH_128 
+axi_bus_t #(.AWS_FPGA_AXI_BUS_DATA_WIDTH(128), .AWS_FPGA_AXI_BUS_ID_WIDTH(8), .AWS_FPGA_AXI_BUS_ADDR_WIDTH(64), .AWS_FPGA_AXI_BUS_LEN_WIDTH(4)) nvdla_dbb_axi_bus();
 `else
 axi_bus_t #(.AWS_FPGA_AXI_BUS_DATA_WIDTH(64), .AWS_FPGA_AXI_BUS_ID_WIDTH(8), .AWS_FPGA_AXI_BUS_ADDR_WIDTH(64), .AWS_FPGA_AXI_BUS_LEN_WIDTH(4)) nvdla_dbb_axi_bus();
 `endif

cl_nvdla/design/cl_nvdla_defines.vh

@@ -38,5 +38,27 @@
 `define VLIB_BYPASS_POWER_CG
 `define NV_FPGA_UNIT
 `define NV_FPGA_FIFOGEN
+`ifdef NV_LARGE
+`define NVDLA_CVSRAM_PRESENT
+`define NVDLA_AXI_WIDTH_256
+`endif
+`ifdef NV_MEDIUM_1024_FULL
+`define NVDLA_CVSRAM_PRESENT
+`define NVDLA_AXI_WIDTH_256
+`endif
+`ifdef NV_MEDIUM_512
+`define NVDLA_AXI_WIDTH_128
+`endif
+`ifdef NV_SMALL_256_FULL
+`define NVDLA_CVSRAM_PRESENT
+`define NVDLA_AXI_WIDTH_64
+`endif
+`ifdef NV_SMALL_256
+`define NVDLA_AXI_WIDTH_64
+`endif
+`ifdef NV_SMALL
+`define NVDLA_AXI_WIDTH_64
+`endif
+
 `endif