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Add riscv64 scalar-path support#250

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carlosqwqqwq wants to merge 1 commit into
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carlosqwqqwq:riscv-rtm
Open

Add riscv64 scalar-path support#250
carlosqwqqwq wants to merge 1 commit into
nfrechette:developfrom
carlosqwqqwq:riscv-rtm

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@carlosqwqqwq

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Why

RTM already has a portable scalar fallback, but it does not currently recognize riscv64 as an explicit architecture in its public detection headers or developer build entrypoints. In addition, intrinsic auto-detection in rtm/math.h relies on host compiler SIMD macros directly, which can leak host x86_64 SSE state into simulated or cross-target riscv64 builds. This patch makes the scalar fallback explicit for RISC-V and hardens feature detection so it is gated by the selected architecture instead of raw host SIMD defines alone.

What changed

  • Update includes/rtm/impl/detect_arch.h to recognize __riscv and define RTM_ARCH_RISCV, RTM_ARCH_RISCV64, or RTM_ARCH_RISCV32 as appropriate.
  • Update includes/rtm/math.h so SSE/AVX intrinsic detection only runs when the selected architecture is x86 or x64, preventing host SIMD leakage into RISC-V builds.
  • Update make.py to accept riscv64 as a CPU target, auto-detect native riscv64 Linux hosts, and reject fake cross-compilation attempts that do not use a real RISC-V compiler/toolchain.
  • Update README.md and docs/getting_started.md to document that riscv64 currently uses RTM's generic scalar path and that cross-compilation should use CMake with a proper RISC-V toolchain file.

Verification

  • Initialized the repository submodules with git submodule update --init --recursive so the test targets could configure normally.
  • Ran native CMake configuration with Ninja:
    • cmake -S . -B build-native -G Ninja -DCPU_INSTRUCTION_SET=x64 -DCMAKE_CXX_STANDARD=11
  • Built the native test targets successfully:
    • cmake --build build-native --parallel 4
  • Ran the native unit test executable directly and confirmed success:
    • build-native/tests/main_generic/rtm_unit_tests.exe
    • Result: All tests passed (6579 assertions in 180 test cases)
  • Compiled a RISC-V smoke-test translation unit under forced __riscv=1 and __riscv_xlen=64 and confirmed the scalar fallback is selected.
  • Preprocessed the same smoke-test translation unit and confirmed that only RTM_ARCH_RISCV, RTM_ARCH_RISCV64, and RTM_NO_INTRINSICS are defined, with no RTM_SSE2_INTRINSICS or RTM_NEON_INTRINSICS.
  • Ran python make.py -cpu riscv64 on a non-RISC-V Windows host and confirmed it now fails fast with an explicit message that make.py only supports native Linux riscv64 hosts and that cross-compilation should use a proper CMake toolchain.
  • Ran a real riscv64 cross configure in dockcross/linux-riscv64:
    • cmake -S . -B build-riscv -G Ninja -DCMAKE_BUILD_TYPE=Release -DCMAKE_SYSTEM_NAME=Linux -DCMAKE_SYSTEM_PROCESSOR=riscv64 -DCMAKE_CXX_COMPILER=/usr/xcc/riscv64-unknown-linux-gnu/bin/riscv64-unknown-linux-gnu-g++ -DCMAKE_C_COMPILER=/usr/xcc/riscv64-unknown-linux-gnu/bin/riscv64-unknown-linux-gnu-gcc -DCMAKE_TRY_COMPILE_TARGET_TYPE=STATIC_LIBRARY -DCPU_INSTRUCTION_SET=riscv64 -DIS_CROSS_COMPILING=ON
  • Built the real riscv64 test targets successfully:
    • cmake --build build-riscv --parallel 4
  • Confirmed the real build compiles both:
    • tests/main_generic/rtm_unit_tests
    • tests/validate_includes/librtm_validate_includes.a
  • Confirmed the real build-riscv/build.ninja contains no -march=native, -mavx*, -msse*, arm_neon, arm_sve, /arch:AVX, or /arch:SSE.
  • Verified the resulting test executable is a real RISC-V ELF:
    • file build-riscv/tests/main_generic/rtm_unit_tests
    • readelf -h build-riscv/tests/main_generic/rtm_unit_tests
  • Ran the full real riscv64 unit test executable under qemu-riscv64:
    • qemu-riscv64 -L /usr/xcc/riscv64-unknown-linux-gnu/riscv64-unknown-linux-gnu/sysroot -E LD_LIBRARY_PATH=/usr/xcc/riscv64-unknown-linux-gnu/riscv64-unknown-linux-gnu/sysroot/lib:/usr/xcc/riscv64-unknown-linux-gnu/riscv64-unknown-linux-gnu/lib build-riscv/tests/main_generic/rtm_unit_tests
    • Result: All tests passed (6579 assertions in 180 test cases)

Notes

This is a conservative portability patch. It does not add a RISC-V SIMD or RVV backend. The goal is to make riscv64 a first-class scalar target and to avoid inheriting host x86_64 intrinsic state during simulated or cross-target validation.

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CLAassistant commented Jun 19, 2026

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