Name		Name	Last commit message	Last commit date
Latest commit History 118 Commits
ALUSTAGE.v		ALUSTAGE.v
ALUSTAGE_tb.v		ALUSTAGE_tb.v
CONTROL.v		CONTROL.v
CONTROL_tb.v		CONTROL_tb.v
DECSTAGE.v		DECSTAGE.v
DECSTAGE_tb.v		DECSTAGE_tb.v
IFSTAGE.v		IFSTAGE.v
IFSTAGE_tb.v		IFSTAGE_tb.v
MEMSTAGE.v		MEMSTAGE.v
MEMSTAGE_tb.v		MEMSTAGE_tb.v
PROCESSOR.v		PROCESSOR.v
PROCESSOR_tb.v		PROCESSOR_tb.v
Program.txt		Program.txt
RAM.v		RAM.v
RAM_tb.v		RAM_tb.v
README.md		README.md
ROM.v		ROM.v
ROM_tb.v		ROM_tb.v
alu.v		alu.v
alu_tb.v		alu_tb.v
dec5to32.v		dec5to32.v
dec5to32_tb.v		dec5to32_tb.v
mux2to1.v		mux2to1.v
mux2to1_5bit.v		mux2to1_5bit.v
mux2to1_5bit_tb.v		mux2to1_5bit_tb.v
mux2to1_tb.v		mux2to1_tb.v
mux32to1.v		mux32to1.v
mux32to1_tb.v		mux32to1_tb.v
pc.v		pc.v
pc_tb.v		pc_tb.v
reg_file.v		reg_file.v
reg_file_tb.v		reg_file_tb.v
register.v		register.v
register_tb.v		register_tb.v
rom.data		rom.data