Analog IC design of high speed serial link transceiver for 10 GbaseKR standard using a 65 nm CMOS process

This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard. The project consists of 4 main sections:

Name		Name	Last commit message	Last commit date
README.md		README.md
[Book] Analog IC design of high speed serial link transceiver for 10 GbaseKR standard using a 65 nm CMOS process.pdf		[Book] Analog IC design of high speed serial link transceiver for 10 GbaseKR standard using a 65 nm CMOS process.pdf
[PPT] Analog IC design of high speed serial link transceiver for 10 GbaseKR standard using a 65 nm CMOS process.pdf		[PPT] Analog IC design of high speed serial link transceiver for 10 GbaseKR standard using a 65 nm CMOS process.pdf
[Report] Analog IC design of high speed serial link transceiver for 10 GbaseKR standard using a 65 nm CMOS process.pdf		[Report] Analog IC design of high speed serial link transceiver for 10 GbaseKR standard using a 65 nm CMOS process.pdf

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