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src/modm/platform/core/cortex 2 files changed +4
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lines changed Original file line number Diff line number Diff line change @@ -204,7 +204,7 @@ def prepare(module, options):
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memories = listify (options [":target" ].get_driver ("core" )["memory" ])
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# Cortex-M0 does not have remappable vector table, so it will remain in Flash
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- if not options [":target" ].has_driver ("core: cortex-m0*" ) :
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+ if options [":target" ].get_driver ("core" )[ "type" ] != " cortex-m0" :
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default_location = "rom"
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if any ((m ["name" ] == "ccm" and "x" in m ["access" ]) or m ["name" ] == "dtcm" for m in memories ):
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default_location = "ram"
Original file line number Diff line number Diff line change @@ -102,10 +102,12 @@ void __modm_startup(void)
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SCB_EnableICache();
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%% endif
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- %% if " m0" not in core
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+ %% if core != "cortex- m0"
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// Set the vector table location
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SCB->VTOR = (uint32_t)__vector_table_{{ vector_table_location }}_start;
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+ %% endif
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+ %% if "m0" not in core
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// Enable trapping of divide by zero for UDIV/SDIV instructions.
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SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
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%% endif
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