[stm32] Add vector table remap to SRAM for Cortex-M0 STM32 devices

Author: chris-durand

src/modm/platform/core/cortex/module.lb

@@ -12,8 +12,11 @@
 # -----------------------------------------------------------------------------
 
 def common_vector_table_location(env):
+    if env.get(":platform:core:vector_table_location", "rom") == "ram":
+        return "ram"
     return env.get(":platform:cortex-m:vector_table_location", "rom")
 
+
 def common_vector_table(env):
     """
     Computes vector table properties:

src/modm/platform/core/stm32/module.lb

@@ -21,13 +21,25 @@ def prepare(module, options):
     if options[":target"].identifier.platform != "stm32":
         return False
 
+    if options[":target"].get_driver("core")["type"] == "cortex-m0":
+        module.add_option(
+            EnumerationOption(
+                name="vector_table_location",
+                description=FileReader("option/vector_table_location.md"),
+                enumeration=["rom", "ram"],
+                default="rom")
+            )
+
     module.depends(":platform:cortex-m")
     return True
 
 
 def build(env):
     target = env[":target"].identifier
-    env.substitutions = {"target": target}
+    env.substitutions = {
+        "target": target,
+        "vector_table_location": env.get(":platform:core:vector_table_location", "rom")
+    }
     env.outbasepath = "modm/src/modm/platform/core"
     # startup helper code
     env.template("startup_platform.c.in")
@@ -74,6 +86,8 @@ def post_build(env):
     env.outbasepath = "modm/link"
 
     linkerscript = "../cortex/ram.ld.in"
+    if env.get(":platform:core:vector_table_location", "rom") == "ram":
+        linkerscript = "ram_remap_vector_table.ld.in"
     for memory in env.substitutions["memories"]:
         if memory["name"] == "ccm":
             if "x" in memory["access"]:

src/modm/platform/core/stm32/module.md

@@ -440,3 +440,55 @@ placed into the 128kB DTCM, but cannot overflow into D1_SRAM section.
     ITCM    │  .vector_ram           │
 0x0000 0000 └────────────────────────┘◄ __itcm_start
 ```
+
+## Static RAM (SRAM) with vector table remap on F0 devices
+
+This memory map is identical to the SRAM default one, except that
+`.vector_ram` is placed at the beginning of SRAM1. It is used on STM32F0
+devices in case the platform-specific vector table relocation option
+`modm:platform:core:vector_table_location` is set to `ram`.
+
+```
+            ┌────────────────────────┐◄ __sram1_end
+            │  +HEAP_SRAM1           │
+            │  .noinit_sram1         │
+            │  .noinit               │
+            │  .faststack            │
+            │  .bss_sram1            │
+            │  .bss                  │
+            │  .data_sram1           │
+            │  .data                 │
+            │  .fastdata             │
+            │  .fastcode             │
+            │  +MAIN_STACK_SIZE      │◄ __main_stack_top
+   SRAM1    │  .vector_ram           │
+0x2000 0000 └────────────────────────┘◄ __sram1_start
+
+            ┌────────────────────────┐◄ __flash_end
+            │        (unused)        │
+            ├────────────────────────┤◄ __rom_end
+            │  .table.heap           │
+            │  .table.copy.extern    │
+   tables   │  .table.zero.extern    │
+            │  .table.copy.intern    │
+            │  .table.zero.intern    │
+            │                        │
+    copy    │  .data_sram1           │
+    only    │  .data                 │
+            │  .fastcode             │
+            │  .fastdata             │
+            │                        │
+            │  .note.gnu.build-id    │
+            │  .assertion            │
+            │  .hardware_init        │
+            │ (.eh_frame)            │
+    read    │ (.ARM.exidx)           │  only with C++ exceptions enabled
+    only    │ (.ARM.extab)           │
+            │  .init_array           │
+            │  .init                 │
+            │  .rodata               │
+            │  .text                 │
+   FLASH    │  .vector_rom           │
+0x0800 0000 └────────────────────────┘◄ __rom_start, __flash_start
+
+```

src/modm/platform/core/stm32/option/vector_table_location.md

@@ -0,0 +1,26 @@
+# Vector table location in ROM or RAM on F0 devices
+
+STM32 devices with a Cortex-M0 core provide a platform-specific method to place
+the interrupt vector table in SRAM although the core does not support vector
+table relocation. It is only available on STM32F0 since all other devices
+can remap the vector table in the Cortex-M core.
+
+When this method is activated the vector table is copied to the start of SRAM1
+by the startup script. The `SYSCFG->CFGR1` register is set to remap the
+beginning of SRAM to the vector table location at `0x0000 0000`.
+
+You can modify the RAM vector table using the CMSIS NVIC functions:
+
+- `void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)`
+- `uint32_t NVIC_GetVector(IRQn_Type IRQn)`
+
+This remapping method allows to easily boot an application from a custom
+bootloader even if the Cortex-M0 core does not support relocation.
+
+For applications that do not modify the vector table at runtime, relocation to
+RAM is not necessary and can save a few hundred bytes of static memory.
+
+!!! warning "On Interrupt Latency"
+    Placing main stack and vector table into the same memory can significantly
+    slow down interrupt latency, since both I-Code and D-Code memory interface
+    need to fetch from the same access port.

src/modm/platform/core/stm32/ram_remap_vector_table.ld.in

@@ -0,0 +1,45 @@
+%% import "../cortex/linker.macros" as linker with context
+{{ linker.copyright() }}
+
+{{ linker.prefix() }}
+%% set table_heap = []
+%% set table_copy = []
+%% set table_zero = []
+
+SECTIONS
+{
+{{ linker.section_rom_start("FLASH") }}
+
+{{ linker.section_vector_rom("FLASH") }}
+
+{{ linker.section_rom("FLASH") }}
+
+{{ linker.section_vector_ram(cont_ram_regions[0].cont_name|upper, table_copy) }}
+
+{{ linker.section_stack(cont_ram_regions[0].cont_name|upper) }}
+
+{{ linker.section_ram(cont_ram_regions[0].cont_name|upper, "FLASH", table_copy, table_zero,
+                      sections_data=["fastdata", "fastcode", "data_" + cont_ram_regions[0].contains[0].name],
+                      sections_bss=["bss_" + cont_ram_regions[0].contains[0].name],
+                      sections_noinit=["faststack"]) }}
+
+{{ linker.all_heap_sections(table_copy, table_zero, table_heap) }}
+
+%% if with_crashcatcher
+    %#
+    /* Bottom of crash stack for `modm:platform:fault` */
+    g_crashCatcherStack = . - 500;
+    %#
+%% endif
+
+%% if linkerscript_sections
+{{ linkerscript_sections | indent(first=True) }}
+    %#
+%% endif
+
+{{ linker.section_tables("FLASH", table_copy, table_zero, table_heap) }}
+
+{{ linker.section_rom_end("FLASH") }}
+
+{{ linker.section_debug() }}
+}

src/modm/platform/core/stm32/startup_platform.c.in

@@ -3,6 +3,7 @@
  * Copyright (c) 2016-2017, Fabian Greif
  * Copyright (c) 2016-2017, 2019, Niklas Hauser
  * Copyright (c) 2021, Raphael Lehmann
+ * Copyright (c) 2021, Christopher Durand
  *
  * This file is part of the modm project.
  *
@@ -71,4 +72,9 @@ __modm_initialize_platform(void)
 	PWR->CR2 |= PWR_CR2_IOSV;
 #endif
 %% endif
+
+%% if vector_table_location == "ram"
+	// Remap SRAM to 0x0 for vector table relocation without VTOR register
+	SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE;
+%% endif
 }