[kernel][lib][arch] Initial version

Author: bherrera

slipstream/kernel/lib/arch/x86/intrin.zig

@@ -0,0 +1,45 @@
+//! Copyright 2025 The Drift Authors. All rights reserved.
+//! Use of this source code is governed by a BSD-style license that can be
+//! found in the LICENSE file.
+
+/// Yield the processor momentarily. This should be used in busy waits.
+pub fn yield() void {
+    asm volatile ("pause");
+}
+
+/// Synchronize all memory accesses of all kinds.
+pub fn deviceMemoryBarrier() void {
+    asm volatile ("mfence" ::: "memory");
+}
+
+/// Synchronize the ordering of all memory accesses wrt other CPUs.
+pub fn threadMemoryBarrier() void {
+    deviceMemoryBarrier();
+}
+
+/// Force the processor to complete all modifications to register state and
+/// memory by previous instructions (including draining any buffered writes)
+/// before the next instruction is fetched.
+pub fn serializeInstructions() void {
+    // [intel/vol3]: 8.3  Serializing Instructions.
+    // [amd/vol2]: 7.6.4  Serializing Instructions.
+    //
+    // `cpuid` is a serializing instruction.
+    var rax: usize = 0;
+    asm volatile ("cpuid"
+        : [rax] "+{ax}" (rax),
+        :
+        : "rbx", "rcx", "rdx"
+    );
+}
+
+/// Return the current CPU cycle count.
+pub fn cycles() u64 {
+    var result: u64 = undefined;
+    asm volatile ("rdtsc"
+        : [result] "={ax}" (result),
+        :
+        : "rdx"
+    );
+    return result;
+}