fixup! [kernel] Fix zig name convetion

Author: bherrera

slipstream/kernel/arch/x86/mp.zig

@@ -67,7 +67,7 @@ pub export var bp_percpu: X86PerCpu = .{
         .rsvd4 = 0,
         .rsvd5 = 0,
         .iomap_base = 0,
-        .tss_bitmap = [_]u8{0} ** (x86.IO_BITMAP_BYTES + 1),
+        .tss_bitmap = [_]u8{0} ** (x86.io_bitmap_bytes + 1),
     },
     .interrupt_stacks = .{
         .nmi = [_]u8{0} ** mp.INTERRUPT_STACK_SIZE,
@@ -186,11 +186,11 @@ export fn initPercpu(cpu_num: CpuNum) callconv(.C) void {
 
     // Assembly code has already set up %gs.base so that this function's own code can use it
     // implicitly for stack-protector or safe-stack.
-    assert.debug_assert(@src(), x86.read_msr(registers.X86_MSR_IA32_GS_BASE) == @intFromPtr(percpu));
+    assert.debug_assert(@src(), x86.readMsr(registers.X86_MSR_IA32_GS_BASE) == @intFromPtr(percpu));
 
     // Set the KERNEL_GS_BASE MSR to 0
     // When we enter user space, this will be populated via a swapgs
-    x86.write_msr(registers.X86_MSR_IA32_KERNEL_GS_BASE, 0);
+    x86.writeMsr(registers.X86_MSR_IA32_KERNEL_GS_BASE, 0);
 }
 
 /// used to set the bootstrap processor's apic_id once the APIC is initialized
@@ -221,11 +221,11 @@ inline fn readPercpuField(comptime T: type, comptime offset: comptime_int) T {
     }
 
     if (@sizeOf(T) == @sizeOf(u32)) {
-        return @bitCast(x86.read_gs_offset32(offset));
+        return @bitCast(x86.readGsOffset32(offset));
     } else {
         // Second static assertion for size validation
         comptime std.debug.assert(@sizeOf(T) == @sizeOf(u64));
-        return @bitCast(x86.read_gs_offset64(offset));
+        return @bitCast(x86.readGsOffset64(offset));
     }
 }
 

slipstream/kernel/arch/x86/x86.zig

@@ -13,7 +13,7 @@ pub const registers = @cImport({
 // have 48 active virtual address bits.  If/when this changes, we need to come
 // back here and rework the code just a bit to handle the multiple possible
 // sizes instead of assuming 48 bits at compile time.
-pub const X86_VADDR_BITS: u8 = 48;
+pub const x86_vaddr_bits: u8 = 48;
 
 // The definition of an x86/64 "canonical" address depends on the number of
 // total meaningful virtual address bits.  The canonical address range is
@@ -25,19 +25,19 @@ pub const X86_VADDR_BITS: u8 = 48;
 // Precompute the mask for the [N - 1, 63] range so we can easily test to see if
 // an address might be a user-mode address ((addr & Mask) == 0), or might be a
 // kernel address ((addr & Mask) == Mask).
-pub const X86_CANONICAL_ADDRESS_MASK: u64 = ~((@as(u64, 1) << (X86_VADDR_BITS - 1)) - 1);
+pub const x86_canonical_address_mask: u64 = ~((@as(u64, 1) << (x86_vaddr_bits - 1)) - 1);
 
-pub const X86_8BYTE_MASK: u32 = 0xFFFFFFFF;
+pub const x86_8byte_mask: u32 = 0xFFFFFFFF;
 
-pub const arch_exception_context = struct {
+pub const ArchExceptionContext = struct {
     frame: *regs.iframe_t,
     cr2: u64,
     //user_synth_code: u32,
     //user_synth_data: u32,
     is_page_fault: bool,
 };
 
-pub const x86_64_context_switch_frame = struct {
+pub const X86_64ContextSwitchFrame = struct {
     r15: u64,
     r14: u64,
     r13: u64,
@@ -47,15 +47,15 @@ pub const x86_64_context_switch_frame = struct {
     rip: u64,
 };
 
-pub const IO_BITMAP_BITS: usize = 65536;
-pub const IO_BITMAP_BYTES: usize = IO_BITMAP_BITS / 8;
-pub const IO_BITMAP_LONGS: usize = IO_BITMAP_BITS / @sizeOf(usize);
+pub const io_bitmap_bits: usize = 65536;
+pub const io_bitmap_bytes: usize = io_bitmap_bits / 8;
+pub const io_bitmap_longs: usize = io_bitmap_bits / @sizeOf(usize);
 
 // Assignment of Interrupt Stack Table entries
-pub const NUM_ASSIGNED_IST_ENTRIES: usize = 3;
-pub const NMI_IST_INDEX: usize = 1;
-pub const MCE_IST_INDEX: usize = 2;
-pub const DBF_IST_INDEX: usize = 3;
+pub const num_assigned_ist_entries: usize = 3;
+pub const nmi_ist_index: usize = 1;
+pub const mce_ist_index: usize = 2;
+pub const dbf_ist_index: usize = 3;
 
 // x86-64 TSS structure
 pub const Tss = extern struct {
@@ -77,7 +77,7 @@ pub const Tss = extern struct {
     rsvd5: u16 align(1),
     iomap_base: u16 align(1),
 
-    tss_bitmap: [IO_BITMAP_BYTES + 1]u8 align(1),
+    tss_bitmap: [io_bitmap_bytes + 1]u8 align(1),
 };
 
 pub inline fn clts() void {
@@ -273,105 +273,105 @@ inline fn getSegmentRegister(comptime reg: SegmentRegister) u16 {
 }
 
 // Convenience wrapper functions for each register
-pub inline fn set_ds(value: u16) void {
+pub inline fn setDs(value: u16) void {
     setSegmentRegister(.ds, value);
 }
 
-pub inline fn get_ds() u16 {
+pub inline fn getDs() u16 {
     return getSegmentRegister(.ds);
 }
 
-pub inline fn set_es(value: u16) void {
+pub inline fn setEs(value: u16) void {
     setSegmentRegister(.es, value);
 }
 
-pub inline fn get_es() u16 {
+pub inline fn getEs() u16 {
     return getSegmentRegister(.es);
 }
 
-pub inline fn set_fs(value: u16) void {
+pub inline fn setFs(value: u16) void {
     setSegmentRegister(.fs, value);
 }
 
-pub inline fn get_fs() u16 {
+pub inline fn getFs() u16 {
     return getSegmentRegister(.fs);
 }
 
-pub inline fn set_gs(value: u16) void {
+pub inline fn setGs(value: u16) void {
     setSegmentRegister(.gs, value);
 }
 
-pub inline fn get_gs() u16 {
+pub inline fn getGs() u16 {
     return getSegmentRegister(.gs);
 }
 
-pub inline fn read_msr(msr_id: u32) u64 {
-    var msr_read_val_lo: u32 = undefined;
-    var msr_read_val_hi: u32 = undefined;
+pub inline fn readMsr(msrId: u32) u64 {
+    var msrReadValLo: u32 = undefined;
+    var msrReadValHi: u32 = undefined;
     asm volatile ("rdmsr"
-        : [lo] "={eax}" (msr_read_val_lo),
-          [hi] "={edx}" (msr_read_val_hi),
-        : [msr] "{ecx}" (msr_id),
+        : [lo] "={eax}" (msrReadValLo),
+          [hi] "={edx}" (msrReadValHi),
+        : [msr] "{ecx}" (msrId),
     );
-    return (@as(u64, msr_read_val_hi) << 32) | msr_read_val_lo;
+    return (@as(u64, msrReadValHi) << 32) | msrReadValLo;
 }
 
-pub inline fn read_msr32(msr_id: u32) u32 {
-    var msr_read_val: u32 = undefined;
+pub inline fn readMsr32(msrId: u32) u32 {
+    var msrReadVal: u32 = undefined;
     asm volatile ("rdmsr"
-        : [val] "={eax}" (msr_read_val),
-        : [msr] "{ecx}" (msr_id),
+        : [val] "={eax}" (msrReadVal),
+        : [msr] "{ecx}" (msrId),
         : "edx"
     );
-    return msr_read_val;
+    return msrReadVal;
 }
 
 // Implemented in assembly.
-pub extern "C" fn read_msr_safe(msr_id: u32, val: *u64) i32;
+pub extern "C" fn readMsrSafe(msrId: u32, val: *u64) i32;
 
-pub inline fn write_msr(msr_id: u32, msr_write_val: u64) void {
+pub inline fn writeMsr(msrId: u32, msrWriteVal: u64) void {
     asm volatile ("wrmsr"
         :
-        : [msr] "{ecx}" (msr_id),
-          [lo] "{eax}" (@as(u32, @truncate(msr_write_val))),
-          [hi] "{edx}" (@as(u32, @truncate(msr_write_val >> 32))),
+        : [msr] "{ecx}" (msrId),
+          [lo] "{eax}" (@as(u32, @truncate(msrWriteVal))),
+          [hi] "{edx}" (@as(u32, @truncate(msrWriteVal >> 32))),
     );
 }
 
-pub inline fn is_paging_enabled() bool {
+pub inline fn isPagingEnabled() bool {
     return (get_cr0() & registers.X86_CR0_PG) != 0;
 }
 
-pub inline fn is_PAE_enabled() bool {
-    if (!is_paging_enabled()) return false;
+pub inline fn isPaeEnabled() bool {
+    if (!isPagingEnabled()) return false;
     return (get_cr4() & registers.X86_CR4_PAE) != 0;
 }
 
-pub inline fn read_gs_offset64(comptime offset: usize) u64 {
+pub inline fn readGsOffset64(comptime offset: usize) u64 {
     var ret: u64 = undefined;
     asm volatile ("movq %%gs:" ++ std.fmt.comptimePrint("{}", .{offset}) ++ ", %[ret]"
         : [ret] "=r" (ret),
     );
     return ret;
 }
 
-pub inline fn write_gs_offset64(comptime offset: usize, val: u64) void {
+pub inline fn writeGsOffset64(comptime offset: usize, val: u64) void {
     asm volatile ("movq %[val], %%gs:" ++ std.fmt.comptimePrint("{}", .{offset})
         :
         : [val] "ir" (val),
         : "memory"
     );
 }
 
-pub inline fn read_gs_offset32(comptime offset: usize) u32 {
+pub inline fn readGsOffset32(comptime offset: usize) u32 {
     var ret: u32 = undefined;
     asm volatile ("movl %%gs:" ++ std.fmt.comptimePrint("{}", .{offset}) ++ ", %[ret]"
         : [ret] "=r" (ret),
     );
     return ret;
 }
 
-pub inline fn write_gs_offset32(comptime offset: usize, val: u32) void {
+pub inline fn writeGsOffset32(comptime offset: usize, val: u32) void {
     asm volatile ("movl %[val], %%gs:" ++ std.fmt.comptimePrint("{}", .{offset})
         :
         : [val] "ir" (val),