virt_mshv_vtl: Separate out CVM and non-CVM deliver_synic_messages

openhcl/virt_mshv_vtl/src/processor/hardware_cvm/mod.rs

@@ -2334,7 +2334,6 @@ impl<B: HardwareIsolatedBacking> UhProcessor<'_, B> {
 
         for vtl in [GuestVtl::Vtl1, GuestVtl::Vtl0] {
             // Process interrupts.
-
             self.update_synic(vtl, false);
 
             B::poll_apic(self, vtl, scan_irr[vtl] || *first_scan_irr)
@@ -2384,6 +2383,40 @@ impl<B: HardwareIsolatedBacking> UhProcessor<'_, B> {
             // Loop around to process the synic again.
         }
     }
+
+    pub(crate) fn deliver_synic_messages(&mut self, vtl: GuestVtl, sints: u16) {
+        let proxied_sints = self.backing.cvm_state().hv[vtl].synic.proxied_sints();
+        let pending_sints =
+            self.inner.message_queues[vtl].post_pending_messages(sints, |sint, message| {
+                if proxied_sints & (1 << sint) != 0 {
+                    if let Some(synic) = self.backing.untrusted_synic_mut() {
+                        synic.post_message(
+                            sint,
+                            message,
+                            &mut self
+                                .partition
+                                .synic_interrupt(self.inner.vp_info.base.vp_index, vtl),
+                        )
+                    } else {
+                        self.partition.hcl.post_message_direct(
+                            self.inner.vp_info.base.vp_index.index(),
+                            sint,
+                            message,
+                        )
+                    }
+                } else {
+                    self.backing.cvm_state_mut().hv[vtl].synic.post_message(
+                        sint,
+                        message,
+                        &mut self
+                            .partition
+                            .synic_interrupt(self.inner.vp_info.base.vp_index, vtl),
+                    )
+                }
+            });
+
+        self.request_sint_notifications(vtl, pending_sints);
+    }
 }
 
 pub(crate) struct XsetbvExitInput {

openhcl/virt_mshv_vtl/src/processor/mod.rs

@@ -18,6 +18,7 @@ cfg_if::cfg_if! {
         use crate::VtlCrash;
         use bitvec::prelude::BitArray;
         use bitvec::prelude::Lsb0;
+        use hv1_emulator::synic::ProcessorSynic;
         use hvdef::HvX64RegisterName;
         use virt::vp::MpState;
         use virt::x86::MsrError;
@@ -186,7 +187,6 @@ mod private {
     use crate::GuestVtl;
     use crate::processor::UhProcessor;
     use hv1_emulator::hv::ProcessorVtlHv;
-    use hv1_emulator::synic::ProcessorSynic;
     use hv1_structs::VtlArray;
     use inspect::InspectMut;
     use std::future::Future;
@@ -260,8 +260,6 @@ mod private {
         fn hv(&self, vtl: GuestVtl) -> Option<&ProcessorVtlHv>;
         fn hv_mut(&mut self, vtl: GuestVtl) -> Option<&mut ProcessorVtlHv>;
 
-        fn untrusted_synic_mut(&mut self) -> Option<&mut ProcessorSynic>;
-
         fn vtl1_inspectable(this: &UhProcessor<'_, Self>) -> bool;
     }
 }
@@ -477,6 +475,8 @@ trait HardwareIsolatedBacking: Backing {
         this: &mut UhProcessor<'_, Self>,
         intercept_control: HvRegisterCrInterceptControl,
     );
+
+    fn untrusted_synic_mut(&mut self) -> Option<&mut ProcessorSynic>;
 }
 
 #[cfg_attr(guest_arch = "aarch64", expect(dead_code))]
@@ -1126,49 +1126,6 @@ impl<'a, T: Backing> UhProcessor<'a, T> {
         .await
     }
 
-    fn deliver_synic_messages(&mut self, vtl: GuestVtl, sints: u16) {
-        let proxied_sints = self
-            .backing
-            .hv(vtl)
-            .as_ref()
-            .map_or(!0, |hv| hv.synic.proxied_sints());
-        let pending_sints =
-            self.inner.message_queues[vtl].post_pending_messages(sints, |sint, message| {
-                if proxied_sints & (1 << sint) != 0 {
-                    if let Some(synic) = self.backing.untrusted_synic_mut().as_mut() {
-                        synic.post_message(
-                            sint,
-                            message,
-                            &mut self
-                                .partition
-                                .synic_interrupt(self.inner.vp_info.base.vp_index, vtl),
-                        )
-                    } else {
-                        self.partition.hcl.post_message_direct(
-                            self.inner.vp_info.base.vp_index.index(),
-                            sint,
-                            message,
-                        )
-                    }
-                } else {
-                    self.backing
-                        .hv_mut(vtl)
-                        .as_mut()
-                        .unwrap()
-                        .synic
-                        .post_message(
-                            sint,
-                            message,
-                            &mut self
-                                .partition
-                                .synic_interrupt(self.inner.vp_info.base.vp_index, vtl),
-                        )
-                }
-            });
-
-        self.request_sint_notifications(vtl, pending_sints);
-    }
-
     #[cfg(guest_arch = "x86_64")]
     fn update_proxy_irr_filter(&mut self, vtl: GuestVtl) {
         assert_eq!(vtl, GuestVtl::Vtl0);

openhcl/virt_mshv_vtl/src/processor/mshv/arm64.rs

@@ -30,7 +30,6 @@ use hcl::UnsupportedGuestVtl;
 use hcl::ioctl;
 use hcl::ioctl::aarch64::MshvArm64;
 use hv1_emulator::hv::ProcessorVtlHv;
-use hv1_emulator::synic::ProcessorSynic;
 use hvdef::HvAarch64PendingEvent;
 use hvdef::HvArm64RegisterName;
 use hvdef::HvArm64ResetType;
@@ -239,10 +238,6 @@ impl BackingPrivate for HypervisorBackedArm64 {
         None
     }
 
-    fn untrusted_synic_mut(&mut self) -> Option<&mut ProcessorSynic> {
-        None
-    }
-
     fn handle_vp_start_enable_vtl_wake(
         _this: &mut UhProcessor<'_, Self>,
         _vtl: GuestVtl,

openhcl/virt_mshv_vtl/src/processor/mshv/mod.rs

@@ -3,6 +3,10 @@
 
 //! Processor support for Microsoft hypervisor-backed partitions.
 
+use crate::HypervisorBacked;
+use crate::UhProcessor;
+use hcl::GuestVtl;
+
 pub mod arm64;
 mod tlb_lock;
 pub mod x64;
@@ -13,3 +17,18 @@ pub(crate) struct VbsIsolatedVtl1State {
     default_vtl_protections: Option<hvdef::HvMapGpaFlags>,
     enable_vtl_protection: bool,
 }
+
+impl UhProcessor<'_, HypervisorBacked> {
+    fn deliver_synic_messages(&mut self, vtl: GuestVtl, sints: u16) {
+        let pending_sints =
+            self.inner.message_queues[vtl].post_pending_messages(sints, |sint, message| {
+                self.partition.hcl.post_message_direct(
+                    self.inner.vp_info.base.vp_index.index(),
+                    sint,
+                    message,
+                )
+            });
+
+        self.request_sint_notifications(vtl, pending_sints);
+    }
+}

openhcl/virt_mshv_vtl/src/processor/mshv/x64.rs

@@ -31,7 +31,6 @@ use hcl::ioctl::ApplyVtlProtectionsError;
 use hcl::ioctl::x64::MshvX64;
 use hcl::protocol;
 use hv1_emulator::hv::ProcessorVtlHv;
-use hv1_emulator::synic::ProcessorSynic;
 use hv1_hypercall::HvRepResult;
 use hv1_structs::VtlSet;
 use hvdef::HV_PAGE_SIZE;
@@ -353,10 +352,6 @@ impl BackingPrivate for HypervisorBackedX86 {
         None
     }
 
-    fn untrusted_synic_mut(&mut self) -> Option<&mut ProcessorSynic> {
-        None
-    }
-
     fn handle_vp_start_enable_vtl_wake(
         _this: &mut UhProcessor<'_, Self>,
         _vtl: GuestVtl,

openhcl/virt_mshv_vtl/src/processor/snp/mod.rs

@@ -359,6 +359,10 @@ impl HardwareIsolatedBacking for SnpBacked {
             true
         })
     }
+
+    fn untrusted_synic_mut(&mut self) -> Option<&mut ProcessorSynic> {
+        None
+    }
 }
 
 /// Partition-wide shared data for SNP VPs.
@@ -577,10 +581,6 @@ impl BackingPrivate for SnpBacked {
         Some(&mut self.cvm.hv[vtl])
     }
 
-    fn untrusted_synic_mut(&mut self) -> Option<&mut ProcessorSynic> {
-        None
-    }
-
     fn handle_vp_start_enable_vtl_wake(
         this: &mut UhProcessor<'_, Self>,
         vtl: GuestVtl,

openhcl/virt_mshv_vtl/src/processor/tdx/mod.rs

@@ -715,6 +715,10 @@ impl HardwareIsolatedBacking for TdxBacked {
             true
         })
     }
+
+    fn untrusted_synic_mut(&mut self) -> Option<&mut ProcessorSynic> {
+        self.untrusted_synic.as_mut()
+    }
 }
 
 /// Partition-wide shared data for TDX VPs.
@@ -1103,10 +1107,6 @@ impl BackingPrivate for TdxBacked {
         Some(&mut self.cvm.hv[vtl])
     }
 
-    fn untrusted_synic_mut(&mut self) -> Option<&mut ProcessorSynic> {
-        self.untrusted_synic.as_mut()
-    }
-
     fn handle_vp_start_enable_vtl_wake(
         this: &mut UhProcessor<'_, Self>,
         vtl: GuestVtl,