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1. eSim eSim Public

   Forked from FOSSEE/eSim

   This repository contain source code for new flow of FreeEDA now know as eSim

   Python

2. core-v-verif core-v-verif Public

   Forked from openhwgroup/core-v-verif

   Functional verification project for the CORE-V family of RISC-V cores.

   Assembly

3. 8-bit_SAR_ADC 8-bit_SAR_ADC Public

   The following repository contains my work on an 8 bit successive approximation register , a research migration project under FOSSEE eSim

   Verilog

4. cva6 cva6 Public

   Forked from openhwgroup/cva6

   The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

   Assembly