interfaces

Contains several interface definitions, currently for:

• AXI4, AXI4-lite and AXI-stream interfaces (modelled after Zynq's AXI interfaces, not really after the standard itself)
• Personality interfaces for Convey (specifically Convey Wolverine)

These should be self-explanatory for the most part. One thing to note is signal renaming -- if the generated Verilog is going to be instantiated somewhere else and needs certain signal names, it's a good idea to rename the signals directly in Chisel so that the generated Verilog uses the expected names. This is also useful for getting interface inference to work in Vivado IP packager (e.g properly recognize an AXI MM master as such). Some of the interfaces here have a renameSignals function, just call it in the module body to do the renaming (sometimes taking in an extra string parameter that becomes part of the name, to distinguish multiple instances of the same interface).