[test-triage] chip_sw_rv_dm_access_after_escalation_reset test

[sha-ron]

Hierarchy of regression failure

Chip Level

Failure Description

The test fails (on earlgrey_1.0.0 branch) during SW compilation:
ERROR: Skipping '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': no such target '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': target 'alert_handler_escalation_test_sim_dv' not declared in package 'sw/device/tests/sim_dv'

Steps to Reproduce

• GitHub Revision: HASH_VALUE
• dvsim invocation command to reproduce the failure, inclusive of build and run seeds:
  ./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i TEST_NAME --build-seed BUILD_SEED --fixed-seed FAILING_SEED --waves fsdb
• Kokoro build number if applicable

Tests with similar or related failures

• Test_name_1
• Test_name_2