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[csrng/rtl] Remove the genreq FIFO from ctr_drbg_gen
Signed-off-by: Florian Glaser <[email protected]>
1 parent d16ce56 commit 9c9ea5d

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-201
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‎hw/ip/csrng/data/csrng.hjson‎

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -758,15 +758,6 @@
758758
This bit will stay set until the next reset.
759759
'''
760760
}
761-
{ bits: "12",
762-
name: "SFIFO_GGENREQ_ERR",
763-
desc: '''
764-
This bit will be set to one when an error has been detected for the
765-
ggenreq FIFO. The type of error is reflected in the type status
766-
bits (bits 28 through 30 of this register).
767-
This bit will stay set until the next reset.
768-
'''
769-
}
770761
{ bits: "13",
771762
name: "SFIFO_GADSTAGE_ERR",
772763
desc: '''

‎hw/ip/csrng/doc/registers.md‎

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -555,12 +555,12 @@ Writing a zero resets this status bit.
555555
Hardware detection of error conditions status register
556556
- Offset: `0x54`
557557
- Reset default: `0x0`
558-
- Reset mask: `0x7ff0fe03`
558+
- Reset mask: `0x7ff0ee03`
559559

560560
### Fields
561561

562562
```wavejson
563-
{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 7}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_CMD_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
563+
{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 7}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_CMD_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
564564
```
565565

566566
| Bits | Type | Reset | Name |
@@ -581,7 +581,7 @@ Hardware detection of error conditions status register
581581
| 15 | ro | 0x0 | [SFIFO_CMDID_ERR](#err_code--sfifo_cmdid_err) |
582582
| 14 | ro | 0x0 | [SFIFO_GGENBITS_ERR](#err_code--sfifo_ggenbits_err) |
583583
| 13 | ro | 0x0 | [SFIFO_GADSTAGE_ERR](#err_code--sfifo_gadstage_err) |
584-
| 12 | ro | 0x0 | [SFIFO_GGENREQ_ERR](#err_code--sfifo_ggenreq_err) |
584+
| 12 | | | Reserved |
585585
| 11 | ro | 0x0 | [SFIFO_GRCSTAGE_ERR](#err_code--sfifo_grcstage_err) |
586586
| 10 | ro | 0x0 | [SFIFO_GBENCACK_ERR](#err_code--sfifo_gbencack_err) |
587587
| 9 | ro | 0x0 | [SFIFO_FINAL_ERR](#err_code--sfifo_final_err) |
@@ -674,12 +674,6 @@ gadstage FIFO. The type of error is reflected in the type status
674674
bits (bits 28 through 30 of this register).
675675
This bit will stay set until the next reset.
676676

677-
### ERR_CODE . SFIFO_GGENREQ_ERR
678-
This bit will be set to one when an error has been detected for the
679-
ggenreq FIFO. The type of error is reflected in the type status
680-
bits (bits 28 through 30 of this register).
681-
This bit will stay set until the next reset.
682-
683677
### ERR_CODE . SFIFO_GRCSTAGE_ERR
684678
This bit will be set to one when an error has been detected for the
685679
grcstage FIFO. The type of error is reflected in the type status

‎hw/ip/csrng/dv/env/csrng_env_pkg.sv‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,6 @@ package csrng_env_pkg;
6161
sfifo_final_error = 3,
6262
sfifo_gbencack_error = 4,
6363
sfifo_grcstage_error = 5,
64-
sfifo_ggenreq_error = 6,
6564
sfifo_gadstage_error = 7,
6665
sfifo_ggenbits_error = 8,
6766
sfifo_cmdid_error = 9,
@@ -85,7 +84,6 @@ package csrng_env_pkg;
8584
sfifo_final_err = 3,
8685
sfifo_gbencack_err = 4,
8786
sfifo_grcstage_err = 5,
88-
sfifo_ggenreq_err = 6,
8987
sfifo_gadstage_err = 7,
9088
sfifo_ggenbits_err = 8,
9189
sfifo_cmdid_err = 9,
@@ -106,7 +104,6 @@ package csrng_env_pkg;
106104
sfifo_final_err_test = 24,
107105
sfifo_gbencack_err_test = 25,
108106
sfifo_grcstage_err_test = 26,
109-
sfifo_ggenreq_err_test = 27,
110107
sfifo_gadstage_err_test = 28,
111108
sfifo_ggenbits_err_test = 29,
112109
sfifo_cmdid_err_test = 30,
@@ -131,7 +128,6 @@ package csrng_env_pkg;
131128
SFIFO_FINAL_ERR = 9,
132129
SFIFO_GBENCACK_ERR = 10,
133130
SFIFO_GRCSTAGE_ERR = 11,
134-
SFIFO_GGENREQ_ERR = 12,
135131
SFIFO_GADSTAGE_ERR = 13,
136132
SFIFO_GGENBITS_ERR = 14,
137133
SFIFO_CMDID_ERR = 15,
@@ -163,7 +159,6 @@ package csrng_env_pkg;
163159
sfifo_cmdid = 0,
164160
sfifo_ggenbits = 1,
165161
sfifo_gadstage = 2,
166-
sfifo_ggenreq = 3,
167162
sfifo_grcstage = 4,
168163
sfifo_gbencack = 5,
169164
sfifo_final = 6,

‎hw/ip/csrng/dv/env/csrng_path_if.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ interface csrng_path_if
1818
"sfifo_cmd", "sfifo_genbits": return {core_path, $sformatf(".gen_cmd_stage[%0d]", app),
1919
".u_csrng_cmd_stage.", fifo_name, "_", which_path};
2020
"sfifo_final": return {core_path, ".u_csrng_ctr_drbg_upd.", fifo_name, "_", which_path};
21-
"sfifo_gbencack", "sfifo_grcstage", "sfifo_ggenreq", "sfifo_gadstage", "sfifo_ggenbits":
21+
"sfifo_gbencack", "sfifo_grcstage", "sfifo_gadstage", "sfifo_ggenbits":
2222
return {core_path,".u_csrng_ctr_drbg_gen.sfifo_", fifo_name.substr(7, fifo_name.len()-1),
2323
"_", which_path};
2424
"sfifo_cmdid": return {core_path, ".u_csrng_block_encrypt.", fifo_name, "_", which_path};

‎hw/ip/csrng/dv/env/seq_lib/csrng_err_vseq.sv‎

Lines changed: 9 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -101,7 +101,7 @@ class csrng_err_vseq extends csrng_base_vseq;
101101

102102
case (cfg.which_err_code) inside
103103
sfifo_cmd_err, sfifo_genbits_err, sfifo_final_err, sfifo_gbencack_err, sfifo_grcstage_err,
104-
sfifo_gadstage_err, sfifo_ggenbits_err, sfifo_cmdid_err, sfifo_ggenreq_err: begin
104+
sfifo_gadstage_err, sfifo_ggenbits_err, sfifo_cmdid_err: begin
105105
fld = csr.get_field_by_name(fld_name);
106106
fifo_base_path = fld_name.substr(0, last_index-1);
107107

@@ -113,17 +113,12 @@ class csrng_err_vseq extends csrng_base_vseq;
113113
`uvm_info(`gfn, $sformatf("Forcing this FIFO error type %s", cfg.which_fifo_err.name()),
114114
UVM_MEDIUM)
115115

116-
if (cfg.which_err_code == sfifo_ggenreq_err) begin
117-
force_all_fifo_errs_exception(fifo_forced_paths, fifo_forced_values, path_exts, fld,
118-
1'b1, cfg.which_fifo_err);
119-
120116
// For sfifo_gadstage_err the down stream FIFO also takes inputs from sources other than
121117
// sfifo_gadstage. To avoid the propagation of undefined data through CSRNG we need to
122118
// force the input of sfifo_gbencack to zero. Otherwise this will cause a lot of assertions
123119
// to trigger and eventually CSRNG will output undefined bits which causes some tlul checks
124120
// to fail.
125-
end else if ((cfg.which_err_code == sfifo_gadstage_err) &&
126-
(cfg.which_fifo_err == fifo_read)) begin
121+
if ((cfg.which_err_code == sfifo_gadstage_err) && (cfg.which_fifo_err == fifo_read)) begin
127122
fifo_forced_path_ds = cfg.csrng_path_vif.fifo_err_path(cfg.which_app_err_alert,
128123
"sfifo_gbencack", "rdata");
129124
uvm_hdl_force(fifo_forced_path_ds, 'b0);
@@ -251,26 +246,20 @@ class csrng_err_vseq extends csrng_base_vseq;
251246
path2 = cfg.csrng_path_vif.fifo_err_path(cfg.which_app_err_alert, fifo_name,
252247
fifo_err_path[1][path_key]);
253248
if (cfg.which_err_code == fifo_write_err) begin
254-
path3 = cfg.csrng_path_vif.fifo_err_path(cfg.which_app_err_alert, fifo_name,
255-
"wdata");
249+
path3 = cfg.csrng_path_vif.fifo_err_path(cfg.which_app_err_alert, fifo_name, "wdata");
256250
end else if (cfg.which_err_code == fifo_read_err) begin
257-
path3 = cfg.csrng_path_vif.fifo_err_path(cfg.which_app_err_alert, fifo_name,
258-
"rdata");
251+
path3 = cfg.csrng_path_vif.fifo_err_path(cfg.which_app_err_alert, fifo_name, "rdata");
259252
end
260253

261254
value1 = fifo_err_value[0][path_key];
262255
value2 = fifo_err_value[1][path_key];
263256

264-
if ((cfg.which_err_code == fifo_read_error) && (cfg.which_fifo == sfifo_ggenreq)) begin
265-
force_fifo_err_exception(path1, path2, 1'b1, 1'b0, 1'b0, fld, 1'b1);
266-
267257
// For sfifo_gadstage the down stream FIFO also takes inputs from sources other than
268258
// sfifo_gadstage. To avoid the propagation of undefined data through CSRNG we need to
269259
// force the input of sfifo_gbencack to zero. Otherwise this will cause a lot of assertions
270260
// to trigger and eventually CSRNG will output undefined bits which causes some tlul checks
271261
// to fail.
272-
end else if ((cfg.which_err_code == fifo_read_error) &&
273-
(cfg.which_fifo == sfifo_gadstage)) begin
262+
if ((cfg.which_err_code == fifo_read_error) && (cfg.which_fifo == sfifo_gadstage)) begin
274263
fifo_forced_path_ds = cfg.csrng_path_vif.fifo_err_path(cfg.which_app_err_alert,
275264
"sfifo_gbencack", "rdata");
276265
uvm_hdl_force(fifo_forced_path_ds, 'b0);
@@ -299,10 +288,10 @@ class csrng_err_vseq extends csrng_base_vseq;
299288
csr_rd(.ptr(ral.err_code), .value(backdoor_err_code_val));
300289
cov_vif.cg_err_code_sample(.err_code(backdoor_err_code_val));
301290
end
302-
sfifo_cmd_err_test, sfifo_genbits_err_test,
303-
sfifo_final_err_test, sfifo_gbencack_err_test, sfifo_grcstage_err_test,
304-
sfifo_ggenreq_err_test, sfifo_gadstage_err_test, sfifo_ggenbits_err_test,
305-
sfifo_cmdid_err_test, cmd_stage_sm_err_test, main_sm_err_test, drbg_cmd_sm_err_test,
291+
sfifo_cmd_err_test, sfifo_genbits_err_test, sfifo_final_err_test,
292+
sfifo_gbencack_err_test, sfifo_grcstage_err_test, sfifo_gadstage_err_test,
293+
sfifo_ggenbits_err_test, sfifo_cmdid_err_test,
294+
cmd_stage_sm_err_test, main_sm_err_test, drbg_cmd_sm_err_test,
306295
drbg_gen_sm_err_test, drbg_updbe_sm_err_test, drbg_updob_sm_err_test, aes_cipher_sm_err_test,
307296
cmd_gen_cnt_err_test, fifo_write_err_test, fifo_read_err_test, fifo_state_err_test: begin
308297
fld = csr.get_field_by_name(fld_name.substr(0, last_index-1));

‎hw/ip/csrng/dv/env/seq_lib/csrng_intr_vseq.sv‎

Lines changed: 4 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -221,21 +221,15 @@ class csrng_intr_vseq extends csrng_base_vseq;
221221

222222
case (cfg.which_fatal_err) inside
223223
sfifo_cmd_error, sfifo_genbits_error, sfifo_final_error, sfifo_gbencack_error,
224-
sfifo_grcstage_error, sfifo_gadstage_error, sfifo_ggenbits_error, sfifo_cmdid_error,
225-
sfifo_ggenreq_error: begin
224+
sfifo_grcstage_error, sfifo_gadstage_error, sfifo_ggenbits_error, sfifo_cmdid_error: begin
226225
fifo_base_path = fld_name.substr(0, last_index-1);
227226

228227
foreach (path_exts[i]) begin
229228
fifo_forced_paths[i] = cfg.csrng_path_vif.fifo_err_path(cfg.NHwApps, fifo_base_path,
230229
path_exts[i]);
231230
end
232-
if (cfg.which_fatal_err == sfifo_ggenreq_error) begin
233-
force_all_fifo_errs_exception(fifo_forced_paths, fifo_forced_values, path_exts,
234-
ral.intr_state.cs_fatal_err, 1'b1, cfg.which_fifo_err);
235-
end else begin
236-
force_all_fifo_errs(fifo_forced_paths, fifo_forced_values, path_exts,
237-
ral.intr_state.cs_fatal_err, 1'b1, cfg.which_fifo_err);
238-
end
231+
force_all_fifo_errs(fifo_forced_paths, fifo_forced_values, path_exts,
232+
ral.intr_state.cs_fatal_err, 1'b1, cfg.which_fifo_err);
239233
end
240234
cmd_stage_sm_error, main_sm_error, drbg_cmd_sm_error, drbg_gen_sm_error, drbg_updbe_sm_error,
241235
drbg_updob_sm_error: begin
@@ -306,12 +300,7 @@ class csrng_intr_vseq extends csrng_base_vseq;
306300
value1 = fifo_err_value[0][path_key];
307301
value2 = fifo_err_value[1][path_key];
308302

309-
if ((cfg.which_fatal_err == fifo_read_error) && (cfg.which_fifo == sfifo_ggenreq)) begin
310-
force_fifo_err_exception(path1, path2, value1, value2, 1'b0, ral.intr_state.cs_fatal_err,
311-
1'b1);
312-
end else begin
313-
force_fifo_err(path1, path2, value1, value2, ral.intr_state.cs_fatal_err, 1'b1);
314-
end
303+
force_fifo_err(path1, path2, value1, value2, ral.intr_state.cs_fatal_err, 1'b1);
315304
end
316305
default: begin
317306
`uvm_fatal(`gfn, "Invalid case! (bug in environment)")

‎hw/ip/csrng/rtl/csrng_core.sv‎

Lines changed: 3 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -136,8 +136,6 @@ module csrng_core import csrng_pkg::*; #(
136136
logic [2:0] ctr_drbg_gen_sfifo_gbencack_err;
137137
logic ctr_drbg_gen_sfifo_grcstage_err_sum;
138138
logic [2:0] ctr_drbg_gen_sfifo_grcstage_err;
139-
logic ctr_drbg_gen_sfifo_ggenreq_err_sum;
140-
logic [2:0] ctr_drbg_gen_sfifo_ggenreq_err;
141139
logic ctr_drbg_gen_sfifo_gadstage_err_sum;
142140
logic [2:0] ctr_drbg_gen_sfifo_gadstage_err;
143141
logic ctr_drbg_gen_sfifo_ggenbits_err_sum;
@@ -420,7 +418,6 @@ module csrng_core import csrng_pkg::*; #(
420418
ctr_drbg_upd_sfifo_final_err_sum ||
421419
ctr_drbg_gen_sfifo_gbencack_err_sum ||
422420
ctr_drbg_gen_sfifo_grcstage_err_sum ||
423-
ctr_drbg_gen_sfifo_ggenreq_err_sum ||
424421
ctr_drbg_gen_sfifo_gadstage_err_sum ||
425422
ctr_drbg_gen_sfifo_ggenbits_err_sum ||
426423
block_encrypt_sfifo_cmdid_err_sum ||
@@ -438,8 +435,6 @@ module csrng_core import csrng_pkg::*; #(
438435
err_code_test_bit[10];
439436
assign ctr_drbg_gen_sfifo_grcstage_err_sum = (|ctr_drbg_gen_sfifo_grcstage_err) ||
440437
err_code_test_bit[11];
441-
assign ctr_drbg_gen_sfifo_ggenreq_err_sum = (|ctr_drbg_gen_sfifo_ggenreq_err) ||
442-
err_code_test_bit[12];
443438
assign ctr_drbg_gen_sfifo_gadstage_err_sum = (|ctr_drbg_gen_sfifo_gadstage_err) ||
444439
err_code_test_bit[13];
445440
assign ctr_drbg_gen_sfifo_ggenbits_err_sum = (|ctr_drbg_gen_sfifo_ggenbits_err) ||
@@ -459,7 +454,6 @@ module csrng_core import csrng_pkg::*; #(
459454
block_encrypt_sfifo_cmdid_err[2] ||
460455
ctr_drbg_gen_sfifo_ggenbits_err[2] ||
461456
ctr_drbg_gen_sfifo_gadstage_err[2] ||
462-
ctr_drbg_gen_sfifo_ggenreq_err[2] ||
463457
ctr_drbg_gen_sfifo_grcstage_err[2] ||
464458
ctr_drbg_gen_sfifo_gbencack_err[2] ||
465459
ctr_drbg_upd_sfifo_final_err[2] ||
@@ -470,7 +464,6 @@ module csrng_core import csrng_pkg::*; #(
470464
block_encrypt_sfifo_cmdid_err[1] ||
471465
ctr_drbg_gen_sfifo_ggenbits_err[1] ||
472466
ctr_drbg_gen_sfifo_gadstage_err[1] ||
473-
ctr_drbg_gen_sfifo_ggenreq_err[1] ||
474467
ctr_drbg_gen_sfifo_grcstage_err[1] ||
475468
ctr_drbg_gen_sfifo_gbencack_err[1] ||
476469
ctr_drbg_upd_sfifo_final_err[1] ||
@@ -481,7 +474,6 @@ module csrng_core import csrng_pkg::*; #(
481474
block_encrypt_sfifo_cmdid_err[0] ||
482475
ctr_drbg_gen_sfifo_ggenbits_err[0] ||
483476
ctr_drbg_gen_sfifo_gadstage_err[0] ||
484-
ctr_drbg_gen_sfifo_ggenreq_err[0] ||
485477
ctr_drbg_gen_sfifo_grcstage_err[0] ||
486478
ctr_drbg_gen_sfifo_gbencack_err[0] ||
487479
ctr_drbg_upd_sfifo_final_err[0] ||
@@ -510,10 +502,6 @@ module csrng_core import csrng_pkg::*; #(
510502
assign hw2reg.err_code.sfifo_grcstage_err.de = cs_enable_fo[13] &&
511503
ctr_drbg_gen_sfifo_grcstage_err_sum;
512504

513-
assign hw2reg.err_code.sfifo_ggenreq_err.d = 1'b1;
514-
assign hw2reg.err_code.sfifo_ggenreq_err.de = cs_enable_fo[14] &&
515-
ctr_drbg_gen_sfifo_ggenreq_err_sum;
516-
517505
assign hw2reg.err_code.sfifo_gadstage_err.d = 1'b1;
518506
assign hw2reg.err_code.sfifo_gadstage_err.de = cs_enable_fo[15] &&
519507
ctr_drbg_gen_sfifo_gadstage_err_sum;
@@ -1403,7 +1391,6 @@ module csrng_core import csrng_pkg::*; #(
14031391

14041392
.fifo_gbencack_err_o(ctr_drbg_gen_sfifo_gbencack_err),
14051393
.fifo_grcstage_err_o(ctr_drbg_gen_sfifo_grcstage_err),
1406-
.fifo_ggenreq_err_o (ctr_drbg_gen_sfifo_ggenreq_err),
14071394
.fifo_gadstage_err_o(ctr_drbg_gen_sfifo_gadstage_err),
14081395
.fifo_ggenbits_err_o(ctr_drbg_gen_sfifo_ggenbits_err)
14091396
);
@@ -1440,8 +1427,9 @@ module csrng_core import csrng_pkg::*; #(
14401427
logic [SeedLen-1:0] unused_gen_rsp_pdata;
14411428
logic unused_state_db_inst_state;
14421429

1443-
assign unused_err_code_test_bit = (|err_code_test_bit[19:16]) || (|err_code_test_bit[8:2]);
1444-
assign unused_enable_fo = cs_enable_fo[42] || (|cs_enable_fo[9:4]);
1430+
assign unused_err_code_test_bit = (|err_code_test_bit[19:16]) || err_code_test_bit[12] ||
1431+
(|err_code_test_bit[8:2]);
1432+
assign unused_enable_fo = cs_enable_fo[42] || cs_enable_fo[14] || (|cs_enable_fo[9:4]);
14451433
assign unused_reg2hw_genbits = (|reg2hw.genbits.q);
14461434
assign unused_int_state_val = (|reg2hw.int_state_val.q);
14471435
assign unused_reseed_interval = reg2hw.reseed_interval.qe;

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