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[dv,clk_mgr] Vendor in clk_mgr DV environment from OT - #698
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This PR will close issue #432 |
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Results of running the regression: Test Results
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The DV templates hardcode earlgrey's four hint clocks (aes, hmac, kmac, otbn) and build signal names from them. Mocha has one hint clock, clk_main_hint, so the generated environment referred to signals that don't exist and wouldn't compile.
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Clock measurement is disabled in mocha, so the hardware holds its config lock open instead of letting software clear it. The randomized CSR tests write to the lock, read back a different value, and fail. Exclude it from the tests that write to it.
clk_mgr has no interrupts, but the testplan still imported the shared interrupt testplan. This added an interrupt test to the V2 regression that doesn't exist, so every dvsim run logged an error about it and the report carried testpoints that could never be covered.
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Clock measurement is disabled in mocha, so any test that tries to exercise it can't pass. Drop the two measurement tests and their testpoints, and skip the measurement checks inside the tests that also cover other things. In place of the dropped checks, the regwen test now tries to enable measurement and confirms the hardware refuses.
Apply two commits from OpenTitan (lowRISC/opentitan#31175) which allows the driver to resume when it encounters items during a reset, instead of getting stuck forever.
Add the upstream fix from OpenTitan (lowRISC/opentitan#31207) which widens the sec_cm alert window from 7 to 8 cycles in cip_lib, since the alert crosses a clock domain and can arrive a cycle late due to metastability.
…it is not built Gate the CLK_CTRL.CONFIG.REGWEN countermeasure, its RTL annotation and its testpoint on ext_clk_bypass, since the register it protects isn't built without it.
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I believe this PR is good to go now. Thanks @tchilikov-semify !
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This PR makes the clk_mgr DV environment build and pass on mocha's configuration. The environment was already generated in the tree; what was missing was adapting it to a single hint clock and to ext_clk_bypass being false.
The regression can be ran with:
dvsim hw/top_chip/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson -i allIt currently passes 610/610.
This PR disables the clock manager measurement tests, since measurement is disabled in mocha.
The DV templates hardcoded earlgrey's four hint clocks, so the generated environment referred to signals that don't exist in mocha and wouldn't compile. Hint clock names are now generated from the config.
Two shared DV bugs were hit along the way, and both were fixed by vendoring in the upstream OpenTitan fixes.
Lastly, the clkmgr register description declared a countermeasure for the external clock regwen, a register that is not built when ext_clk_bypass is false. That countermeasure, its RTL annotation and its testpoint are now gated on ext_clk_bypass.