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[AArch64] Improve lowering of scalar abs(sub(a, b)). #151180

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Merged
merged 6 commits into from
Aug 6, 2025
Merged

[AArch64] Improve lowering of scalar abs(sub(a, b)). #151180

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c68c342
[AArch64] Improve lowering of scalar abs(sub(a, b)).
rj-jesus Jul 28, 2025
7336546
Combine subs(sub(a,b), 0) -> subs(a,b) in performCSELCombine.
rj-jesus Jul 30, 2025
e8efeab
Update tests after rebase.
rj-jesus Jul 30, 2025
cba370b
Simplify performNegCSelCombine changes.
rj-jesus Jul 30, 2025
78619a5
Combine Cond and Sub with Subs.
rj-jesus Jul 31, 2025
1741900
Revert performNegCSelCombine-related changes.
rj-jesus Jul 31, 2025
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23 changes: 23 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -25464,6 +25464,29 @@ static SDValue performCSELCombine(SDNode *N,
}
}

// CSEL a, b, cc, SUBS(SUB(x,y), 0) -> CSEL a, b, cc, SUBS(x,y) if cc doesn't
// use overflow flags, to avoid the comparison with zero. In case of success,
// this also replaces the original SUB(x,y) with the newly created SUBS(x,y).
// NOTE: Perhaps in the future use performFlagSettingCombine to replace SUB
// nodes with their SUBS equivalent as is already done for other flag-setting
// operators, in which case doing the replacement here becomes redundant.
if (Cond.getOpcode() == AArch64ISD::SUBS && Cond->hasNUsesOfValue(1, 1) &&
isNullConstant(Cond.getOperand(1))) {
SDValue Sub = Cond.getOperand(0);
AArch64CC::CondCode CC =
static_cast<AArch64CC::CondCode>(N->getConstantOperandVal(2));
if (Sub.getOpcode() == ISD::SUB &&
(CC == AArch64CC::EQ || CC == AArch64CC::NE || CC == AArch64CC::MI ||
CC == AArch64CC::PL)) {
SDLoc DL(N);
SDValue Subs = DAG.getNode(AArch64ISD::SUBS, DL, Cond->getVTList(),
Sub.getOperand(0), Sub.getOperand(1));
DCI.CombineTo(Sub.getNode(), Subs);
DCI.CombineTo(Cond.getNode(), Subs, Subs.getValue(1));
return SDValue(N, 0);
}
}

// CSEL (LASTB P, Z), X, NE(ANY P) -> CLASTB P, X, Z
if (SDValue CondLast = foldCSELofLASTB(N, DAG))
return CondLast;
Expand Down
15 changes: 5 additions & 10 deletions llvm/test/CodeGen/AArch64/abds-neg.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,7 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_ext_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, sxtb
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%aext = sext i8 %a to i64
Expand All @@ -26,8 +25,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i8_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, sxth
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%aext = sext i8 %a to i64
Expand All @@ -43,8 +41,7 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_ext_i8_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, sxtb
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%aext = sext i8 %a to i64
Expand All @@ -60,8 +57,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, sxth
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%aext = sext i16 %a to i64
Expand Down Expand Up @@ -93,8 +89,7 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i16_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, sxth
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%aext = sext i16 %a to i64
Expand Down
36 changes: 12 additions & 24 deletions llvm/test/CodeGen/AArch64/abds.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,7 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_ext_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, sxtb
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%aext = sext i8 %a to i64
Expand All @@ -25,8 +24,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i8_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, sxth
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%aext = sext i8 %a to i64
Expand All @@ -41,8 +39,7 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_ext_i8_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, sxtb
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%aext = sext i8 %a to i64
Expand All @@ -57,8 +54,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, sxth
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%aext = sext i16 %a to i64
Expand Down Expand Up @@ -88,8 +84,7 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i16_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, sxth
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%aext = sext i16 %a to i64
Expand Down Expand Up @@ -215,8 +210,7 @@ define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_minmax_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, sxtb
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%min = call i8 @llvm.smin.i8(i8 %a, i8 %b)
Expand All @@ -229,8 +223,7 @@ define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_minmax_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, sxth
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%min = call i16 @llvm.smin.i16(i16 %a, i16 %b)
Expand Down Expand Up @@ -287,8 +280,7 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_cmp_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, sxtb
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp sgt i8 %a, %b
Expand All @@ -302,8 +294,7 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_cmp_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, sxth
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp sge i16 %a, %b
Expand Down Expand Up @@ -508,9 +499,8 @@ define i64 @vector_legalized(i16 %a, i16 %b) {
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxth
; CHECK-NEXT: subs w8, w8, w1, sxth
; CHECK-NEXT: addp d0, v0.2d
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: cneg w8, w8, mi
; CHECK-NEXT: fmov x9, d0
; CHECK-NEXT: add x0, x9, x8
Expand All @@ -533,8 +523,7 @@ define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_select_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, sxtb
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp slt i8 %a, %b
Expand All @@ -548,8 +537,7 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_select_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, sxth
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp sle i16 %a, %b
Expand Down
15 changes: 5 additions & 10 deletions llvm/test/CodeGen/AArch64/abdu-neg.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,7 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_ext_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: sub w8, w8, w1, uxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, uxtb
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%aext = zext i8 %a to i64
Expand All @@ -26,8 +25,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i8_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: sub w8, w8, w1, uxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, uxth
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%aext = zext i8 %a to i64
Expand All @@ -43,8 +41,7 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_ext_i8_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: sub w8, w8, w1, uxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, uxtb
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%aext = zext i8 %a to i64
Expand All @@ -60,8 +57,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: sub w8, w8, w1, uxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, uxth
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%aext = zext i16 %a to i64
Expand Down Expand Up @@ -93,8 +89,7 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i16_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: sub w8, w8, w1, uxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, uxth
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%aext = zext i16 %a to i64
Expand Down
38 changes: 13 additions & 25 deletions llvm/test/CodeGen/AArch64/abdu.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,7 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_ext_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: sub w8, w8, w1, uxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, uxtb
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%aext = zext i8 %a to i64
Expand All @@ -25,8 +24,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i8_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: sub w8, w8, w1, uxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, uxth
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%aext = zext i8 %a to i64
Expand All @@ -41,8 +39,7 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_ext_i8_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: sub w8, w8, w1, uxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, uxtb
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%aext = zext i8 %a to i64
Expand All @@ -57,8 +54,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: sub w8, w8, w1, uxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, uxth
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%aext = zext i16 %a to i64
Expand Down Expand Up @@ -88,8 +84,7 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i16_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: sub w8, w8, w1, uxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, uxth
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%aext = zext i16 %a to i64
Expand Down Expand Up @@ -219,8 +214,7 @@ define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_minmax_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: sub w8, w8, w1, uxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, uxtb
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%min = call i8 @llvm.umin.i8(i8 %a, i8 %b)
Expand All @@ -233,8 +227,7 @@ define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_minmax_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: sub w8, w8, w1, uxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, uxth
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
Expand Down Expand Up @@ -293,8 +286,7 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_cmp_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: sub w8, w8, w1, uxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, uxtb
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp ugt i8 %a, %b
Expand All @@ -308,8 +300,7 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_cmp_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: sub w8, w8, w1, uxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, uxth
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp uge i16 %a, %b
Expand Down Expand Up @@ -373,10 +364,9 @@ define i64 @vector_legalized(i16 %a, i16 %b) {
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: sub w8, w8, w1, uxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: addp d0, v0.2d
; CHECK-NEXT: subs w8, w8, w1, uxth
; CHECK-NEXT: cneg w8, w8, mi
; CHECK-NEXT: addp d0, v0.2d
; CHECK-NEXT: fmov x9, d0
; CHECK-NEXT: add x0, x9, x8
; CHECK-NEXT: ret
Expand All @@ -398,8 +388,7 @@ define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_select_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: sub w8, w8, w1, uxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, uxtb
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp ult i8 %a, %b
Expand All @@ -413,8 +402,7 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_select_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: sub w8, w8, w1, uxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: subs w8, w8, w1, uxth
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp ule i16 %a, %b
Expand Down
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