Skip to content

[AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) #146329

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Open
wants to merge 2 commits into
base: users/jthackray/unify-tests1
Choose a base branch
from
Open

[AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) #146329

wants to merge 2 commits into from

Conversation

jthackray
Copy link
Contributor

@jthackray jthackray commented Jun 30, 2025 •
edited
Loading

This is a series of patches (2/4) to unify assembly/disassembly of recent AArch64 tests into a single file. The aim is to improve consistency, so that all instructions and system registers are thoroughly tested, and future test cases will be in a unified format.

This patch:

  • removes .txt tests which have only one feature required
  • makes the .s tests have a roundabout run line to test both encoding and assembly
  • creates diagnostic tests when needed
  • fixes naming convention of tests

See also #146328, #146330 and #146331.

@llvmbot llvmbot added backend:AArch64 mc Machine (object) code labels Jun 30, 2025
@llvmbot
Copy link
Member

llvmbot commented Jun 30, 2025 •
edited
Loading

@llvm/pr-subscribers-mc

@llvm/pr-subscribers-backend-aarch64

Author: Jonathan Thackray (jthackray)

Changes

This is a series of patches (2/4) to unify assembly/disassembly of recent AArch64 tests into a single file. The aim is to improve consistency, so that all instructions and system registers are thoroughly tested, and future test cases will be in a unified format.

This patch:

  • removes .txt tests which have only one feature required
  • makes the .s tests have a roundabout run line to test both encoding and assembly
  • creates diagnostic tests when needed
  • fixes naming convention of tests

Patch is 52.94 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/146329.diff

13 Files Affected:

  • (modified) llvm/test/MC/AArch64/armv9.2a-mec.s (+117-55)
  • (removed) llvm/test/MC/AArch64/armv9.4-lse128.s (-98)
  • (modified) llvm/test/MC/AArch64/armv9.4a-gcs.s (+143-55)
  • (added) llvm/test/MC/AArch64/armv9.4a-lse128-diagnostics.s (+17)
  • (added) llvm/test/MC/AArch64/armv9.4a-lse128.s (+138)
  • (modified) llvm/test/MC/AArch64/armv9.5a-cpa.s (+63-26)
  • (added) llvm/test/MC/AArch64/armv9.6a-mpam-diagnostics.s (+5)
  • (modified) llvm/test/MC/AArch64/armv9.6a-mpam.s (+58-22)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv9.4a-gcs.txt (-90)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv9.4a-lse128.txt (-98)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv9.5a-cpa.txt (-42)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv9.6a-mpam.txt (-50)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt (-54)
diff --git a/llvm/test/MC/AArch64/armv9.2a-mec.s b/llvm/test/MC/AArch64/armv9.2a-mec.s
index 42e4bf732086e..c747886f7ec3b 100644
--- a/llvm/test/MC/AArch64/armv9.2a-mec.s
+++ b/llvm/test/MC/AArch64/armv9.2a-mec.s
@@ -1,55 +1,117 @@
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mec < %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=CHECK-NO-MEC %s
-
-          mrs x0, MECIDR_EL2
-// CHECK: mrs   x0, MECIDR_EL2       // encoding: [0xe0,0xa8,0x3c,0xd5]
-// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
-          mrs x0, MECID_P0_EL2
-// CHECK: mrs   x0, MECID_P0_EL2      // encoding: [0x00,0xa8,0x3c,0xd5]
-// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
-          mrs x0, MECID_A0_EL2
-// CHECK: mrs   x0, MECID_A0_EL2      // encoding: [0x20,0xa8,0x3c,0xd5]
-// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
-          mrs x0, MECID_P1_EL2
-// CHECK: mrs   x0, MECID_P1_EL2      // encoding: [0x40,0xa8,0x3c,0xd5]
-// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
-          mrs x0, MECID_A1_EL2
-// CHECK: mrs   x0, MECID_A1_EL2      // encoding: [0x60,0xa8,0x3c,0xd5]
-// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
-          mrs x0, VMECID_P_EL2
-// CHECK: mrs   x0, VMECID_P_EL2     // encoding: [0x00,0xa9,0x3c,0xd5]
-// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
-          mrs x0, VMECID_A_EL2
-// CHECK: mrs   x0, VMECID_A_EL2     // encoding: [0x20,0xa9,0x3c,0xd5]
-// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
-          mrs x0, MECID_RL_A_EL3
-// CHECK: mrs   x0, MECID_RL_A_EL3   // encoding: [0x20,0xaa,0x3e,0xd5]
-// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
-          msr MECID_P0_EL2,    x0
-// CHECK: msr   MECID_P0_EL2, x0      // encoding: [0x00,0xa8,0x1c,0xd5]
-// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
-          msr MECID_A0_EL2,    x0
-// CHECK: msr   MECID_A0_EL2, x0      // encoding: [0x20,0xa8,0x1c,0xd5]
-// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
-          msr MECID_P1_EL2,    x0
-// CHECK: msr   MECID_P1_EL2, x0      // encoding: [0x40,0xa8,0x1c,0xd5]
-// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
-          msr MECID_A1_EL2,    x0
-// CHECK: msr   MECID_A1_EL2, x0      // encoding: [0x60,0xa8,0x1c,0xd5]
-// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
-          msr VMECID_P_EL2,   x0
-// CHECK: msr   VMECID_P_EL2, x0     // encoding: [0x00,0xa9,0x1c,0xd5]
-// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
-          msr VMECID_A_EL2,   x0
-// CHECK: msr   VMECID_A_EL2, x0     // encoding: [0x20,0xa9,0x1c,0xd5]
-// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
-          msr MECID_RL_A_EL3, x0
-// CHECK: msr   MECID_RL_A_EL3, x0   // encoding: [0x20,0xaa,0x1e,0xd5]
-// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
-
-          dc cigdpae, x0
-// CHECK: dc cigdpae, x0             // encoding: [0xe0,0x7e,0x0c,0xd5]
-// CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIGDPAE requires: mec
-          dc cipae, x0
-// CHECK: dc cipae, x0               // encoding: [0x00,0x7e,0x0c,0xd5]
-// CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIPAE requires: mec
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mec < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mec < %s \
+// RUN:        | llvm-objdump -d --mattr=+mec --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mec < %s \
+// RUN:   | llvm-objdump -d --mattr=-mec --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mec < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+mec -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+
+mrs x0, MECIDR_EL2
+// CHECK-INST: mrs x0, MECIDR_EL2
+// CHECK-ENCODING: encoding: [0xe0,0xa8,0x3c,0xd5]
+// CHECK-ERROR: error: expected readable system register
+// CHECK-UNKNOWN:  d53ca8e0 mrs x0, S3_4_C10_C8_7
+
+mrs x0, MECID_P0_EL2
+// CHECK-INST: mrs x0, MECID_P0_EL2
+// CHECK-ENCODING: encoding: [0x00,0xa8,0x3c,0xd5]
+// CHECK-ERROR: error: expected readable system register
+// CHECK-UNKNOWN:  d53ca800 mrs x0, S3_4_C10_C8_0
+
+mrs x0, MECID_A0_EL2
+// CHECK-INST: mrs x0, MECID_A0_EL2
+// CHECK-ENCODING: encoding: [0x20,0xa8,0x3c,0xd5]
+// CHECK-ERROR: error: expected readable system register
+// CHECK-UNKNOWN:  d53ca820 mrs x0, S3_4_C10_C8_1
+
+mrs x0, MECID_P1_EL2
+// CHECK-INST: mrs x0, MECID_P1_EL2
+// CHECK-ENCODING: encoding: [0x40,0xa8,0x3c,0xd5]
+// CHECK-ERROR: error: expected readable system register
+// CHECK-UNKNOWN:  d53ca840 mrs x0, S3_4_C10_C8_2
+
+mrs x0, MECID_A1_EL2
+// CHECK-INST: mrs x0, MECID_A1_EL2
+// CHECK-ENCODING: encoding: [0x60,0xa8,0x3c,0xd5]
+// CHECK-ERROR: error: expected readable system register
+// CHECK-UNKNOWN:  d53ca860 mrs x0, S3_4_C10_C8_3
+
+mrs x0, VMECID_P_EL2
+// CHECK-INST: mrs x0, VMECID_P_EL2
+// CHECK-ENCODING: encoding: [0x00,0xa9,0x3c,0xd5]
+// CHECK-ERROR: error: expected readable system register
+// CHECK-UNKNOWN:  d53ca900 mrs x0, S3_4_C10_C9_0
+
+mrs x0, VMECID_A_EL2
+// CHECK-INST: mrs x0, VMECID_A_EL2
+// CHECK-ENCODING: encoding: [0x20,0xa9,0x3c,0xd5]
+// CHECK-ERROR: error: expected readable system register
+// CHECK-UNKNOWN:  d53ca920 mrs x0, S3_4_C10_C9_1
+
+mrs x0, MECID_RL_A_EL3
+// CHECK-INST: mrs x0, MECID_RL_A_EL3
+// CHECK-ENCODING: encoding: [0x20,0xaa,0x3e,0xd5]
+// CHECK-ERROR: error: expected readable system register
+// CHECK-UNKNOWN:  d53eaa20 mrs x0, S3_6_C10_C10_1
+
+msr MECID_P0_EL2,    x0
+// CHECK-INST: msr MECID_P0_EL2, x0
+// CHECK-ENCODING: encoding: [0x00,0xa8,0x1c,0xd5]
+// CHECK-ERROR: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51ca800 msr S3_4_C10_C8_0, x0
+
+msr MECID_A0_EL2,    x0
+// CHECK-INST: msr MECID_A0_EL2, x0
+// CHECK-ENCODING: encoding: [0x20,0xa8,0x1c,0xd5]
+// CHECK-ERROR: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51ca820 msr S3_4_C10_C8_1, x0
+
+msr MECID_P1_EL2,    x0
+// CHECK-INST: msr MECID_P1_EL2, x0
+// CHECK-ENCODING: encoding: [0x40,0xa8,0x1c,0xd5]
+// CHECK-ERROR: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51ca840 msr S3_4_C10_C8_2, x0
+
+msr MECID_A1_EL2,    x0
+// CHECK-INST: msr MECID_A1_EL2, x0
+// CHECK-ENCODING: encoding: [0x60,0xa8,0x1c,0xd5]
+// CHECK-ERROR: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51ca860 msr S3_4_C10_C8_3, x0
+
+msr VMECID_P_EL2,   x0
+// CHECK-INST: msr VMECID_P_EL2, x0
+// CHECK-ENCODING: encoding: [0x00,0xa9,0x1c,0xd5]
+// CHECK-ERROR: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51ca900 msr S3_4_C10_C9_0, x0
+
+msr VMECID_A_EL2,   x0
+// CHECK-INST: msr VMECID_A_EL2, x0
+// CHECK-ENCODING: encoding: [0x20,0xa9,0x1c,0xd5]
+// CHECK-ERROR: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51ca920 msr S3_4_C10_C9_1, x0
+
+msr MECID_RL_A_EL3, x0
+// CHECK-INST: msr MECID_RL_A_EL3, x0
+// CHECK-ENCODING: encoding: [0x20,0xaa,0x1e,0xd5]
+// CHECK-ERROR: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51eaa20 msr S3_6_C10_C10_1, x0
+
+dc cigdpae, x0
+// CHECK-INST: dc cigdpae, x0
+// CHECK-ENCODING: encoding: [0xe0,0x7e,0x0c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:4: error: DC CIGDPAE requires: mec
+// CHECK-UNKNOWN:  d50c7ee0 sys #4, c7, c14, #7, x0
+
+dc cipae, x0
+// CHECK-INST: dc cipae, x0
+// CHECK-ENCODING: encoding: [0x00,0x7e,0x0c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:4: error: DC CIPAE requires: mec
+// CHECK-UNKNOWN:  d50c7e00 sys #4, c7, c14, #0, x0
diff --git a/llvm/test/MC/AArch64/armv9.4-lse128.s b/llvm/test/MC/AArch64/armv9.4-lse128.s
deleted file mode 100644
index a639278ec8263..0000000000000
--- a/llvm/test/MC/AArch64/armv9.4-lse128.s
+++ /dev/null
@@ -1,98 +0,0 @@
-// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr +lse128 %s 2>%t | FileCheck %s
-// RUN: FileCheck %s --input-file=%t --check-prefix=ERROR-INVALID-OP
-// RUN: not llvm-mc -triple aarch64 -show-encoding %s 2>&1 | FileCheck --check-prefix=ERROR-NO-LSE128 %s
-
-ldclrp   x1, x2, [x11]
-// CHECK: ldclrp x1, x2, [x11]                   // encoding: [0x61,0x11,0x22,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-ldclrp   x21, x22, [sp]
-// CHECK: ldclrp x21, x22, [sp]                  // encoding: [0xf5,0x13,0x36,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-ldclrpa  x1, x2, [x11]
-// CHECK: ldclrpa x1, x2, [x11]                   // encoding: [0x61,0x11,0xa2,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-ldclrpa  x21, x22, [sp]
-// CHECK: ldclrpa x21, x22, [sp]                  // encoding: [0xf5,0x13,0xb6,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-ldclrpal x1, x2, [x11]
-// CHECK: ldclrpal x1, x2, [x11]                   // encoding: [0x61,0x11,0xe2,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-ldclrpal x21, x22, [sp]
-// CHECK: ldclrpal x21, x22, [sp]                  // encoding: [0xf5,0x13,0xf6,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-ldclrpl  x1, x2, [x11]
-// CHECK: ldclrpl x1, x2, [x11]                   // encoding: [0x61,0x11,0x62,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-ldclrpl  x21, x22, [sp]
-// CHECK: ldclrpl x21, x22, [sp]                  // encoding: [0xf5,0x13,0x76,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-ldclrpl  x22, xzr, [sp]
-// ERROR-INVALID-OP: [[@LINE-1]]:15: error: invalid operand for instruction
-// ERROR-NO-LSE128: error: invalid operand for instruction
-ldclrpl  xzr, x22, [sp]
-// ERROR-INVALID-OP: [[@LINE-1]]:10: error: invalid operand for instruction
-// ERROR-NO-LSE128: error: invalid operand for instruction
-
-ldsetp   x1, x2, [x11]
-// CHECK: ldsetp x1, x2, [x11]                   // encoding: [0x61,0x31,0x22,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-ldsetp   x21, x22, [sp]
-// CHECK: ldsetp x21, x22, [sp]                  // encoding: [0xf5,0x33,0x36,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-ldsetpa  x1, x2, [x11]
-// CHECK: ldsetpa x1, x2, [x11]                   // encoding: [0x61,0x31,0xa2,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-ldsetpa  x21, x22, [sp]
-// CHECK: ldsetpa x21, x22, [sp]                  // encoding: [0xf5,0x33,0xb6,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-ldsetpal x1, x2, [x11]
-// CHECK: ldsetpal x1, x2, [x11]                   // encoding: [0x61,0x31,0xe2,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-ldsetpal x21, x22, [sp]
-// CHECK: ldsetpal x21, x22, [sp]                  // encoding: [0xf5,0x33,0xf6,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-ldsetpl  x1, x2, [x11]
-// CHECK: ldsetpl x1, x2, [x11]                   // encoding: [0x61,0x31,0x62,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-ldsetpl  x21, x22, [sp]
-// CHECK: ldsetpl x21, x22, [sp]                  // encoding: [0xf5,0x33,0x76,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-ldsetpl  x22, xzr, [sp]
-// ERROR-INVALID-OP: [[@LINE-1]]:15: error: invalid operand for instruction
-// ERROR-NO-LSE128: error: invalid operand for instruction
-ldsetpl  xzr, x22, [sp]
-// ERROR-INVALID-OP: [[@LINE-1]]:10: error: invalid operand for instruction
-// ERROR-NO-LSE128: error: invalid operand for instruction
-
-
-swpp     x1, x2, [x11]
-// CHECK: swpp x1, x2, [x11]                   // encoding: [0x61,0x81,0x22,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-swpp     x21, x22, [sp]
-// CHECK: swpp x21, x22, [sp]                  // encoding: [0xf5,0x83,0x36,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-swppa    x1, x2, [x11]
-// CHECK: swppa x1, x2, [x11]                   // encoding: [0x61,0x81,0xa2,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-swppa    x21, x22, [sp]
-// CHECK: swppa x21, x22, [sp]                  // encoding: [0xf5,0x83,0xb6,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-swppal   x1, x2, [x11]
-// CHECK: swppal x1, x2, [x11]                   // encoding: [0x61,0x81,0xe2,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-swppal   x21, x22, [sp]
-// CHECK: swppal x21, x22, [sp]                  // encoding: [0xf5,0x83,0xf6,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-swppl    x1, x2, [x11]
-// CHECK: swppl x1, x2, [x11]                   // encoding: [0x61,0x81,0x62,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-swppl    x21, x22, [sp]
-// CHECK: swppl x21, x22, [sp]                  // encoding: [0xf5,0x83,0x76,0x19]
-// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
-swppl    x22, xzr, [sp]
-// ERROR-INVALID-OP: [[@LINE-1]]:15: error: invalid operand for instruction
-// ERROR-NO-LSE128: error: invalid operand for instruction
-swppl    xzr, x22, [sp]
-// ERROR-INVALID-OP: [[@LINE-1]]:10: error: invalid operand for instruction
-// ERROR-NO-LSE128: error: invalid operand for instruction
-
diff --git a/llvm/test/MC/AArch64/armv9.4a-gcs.s b/llvm/test/MC/AArch64/armv9.4a-gcs.s
index b4af9b5dcb10c..d6ac23dc2174d 100644
--- a/llvm/test/MC/AArch64/armv9.4a-gcs.s
+++ b/llvm/test/MC/AArch64/armv9.4a-gcs.s
@@ -1,115 +1,203 @@
-// RUN: llvm-mc -triple aarch64 -mattr +gcs -show-encoding %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64 -show-encoding %s 2>%t | FileCheck %s --check-prefix=NO-GCS
-// RUN: FileCheck --check-prefix=ERROR-NO-GCS %s < %t
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+gcs < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+gcs < %s \
+// RUN:        | llvm-objdump -d --mattr=+gcs --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+gcs < %s \
+// RUN:   | llvm-objdump -d --mattr=-gcs --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+gcs < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+gcs -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
 
 msr GCSCR_EL1, x0
+// CHECK-INST: msr GCSCR_EL1, x0
+// CHECK-ENCODING: encoding: [0x00,0x25,0x18,0xd5]
+// CHECK-UNKNOWN:  d5182500 msr GCSCR_EL1, x0
+
 mrs x1, GCSCR_EL1
-// CHECK: msr     GCSCR_EL1, x0                   // encoding: [0x00,0x25,0x18,0xd5]
-// CHECK: mrs     x1, GCSCR_EL1                   // encoding: [0x01,0x25,0x38,0xd5]
+// CHECK-INST: mrs x1, GCSCR_EL1
+// CHECK-ENCODING: encoding: [0x01,0x25,0x38,0xd5]
+// CHECK-UNKNOWN:  d5382501 mrs x1, GCSCR_EL1
 
 msr GCSPR_EL1, x2
+// CHECK-INST: msr GCSPR_EL1, x2
+// CHECK-ENCODING: encoding: [0x22,0x25,0x18,0xd5]
+// CHECK-UNKNOWN:  d5182522 msr GCSPR_EL1, x2
+
 mrs x3, GCSPR_EL1
-// CHECK: msr     GCSPR_EL1, x2                   // encoding: [0x22,0x25,0x18,0xd5]
-// CHECK: mrs     x3, GCSPR_EL1                   // encoding: [0x23,0x25,0x38,0xd5]
+// CHECK-INST: mrs x3, GCSPR_EL1
+// CHECK-ENCODING: encoding: [0x23,0x25,0x38,0xd5]
+// CHECK-UNKNOWN:  d5382523 mrs x3, GCSPR_EL1
 
 msr GCSCRE0_EL1, x4
+// CHECK-INST: msr GCSCRE0_EL1, x4
+// CHECK-ENCODING: encoding: [0x44,0x25,0x18,0xd5]
+// CHECK-UNKNOWN:  d5182544 msr GCSCRE0_EL1, x4
+
 mrs x5, GCSCRE0_EL1
-// CHECK: msr     GCSCRE0_EL1, x4                 // encoding: [0x44,0x25,0x18,0xd5]
-// CHECK: mrs     x5, GCSCRE0_EL1                 // encoding: [0x45,0x25,0x38,0xd5]
+// CHECK-INST: mrs x5, GCSCRE0_EL1
+// CHECK-ENCODING: encoding: [0x45,0x25,0x38,0xd5]
+// CHECK-UNKNOWN:  d5382545 mrs x5, GCSCRE0_EL1
 
 msr GCSPR_EL0, x6
+// CHECK-INST: msr GCSPR_EL0, x6
+// CHECK-ENCODING: encoding: [0x26,0x25,0x1b,0xd5]
+// CHECK-UNKNOWN:  d51b2526 msr GCSPR_EL0, x6
+
 mrs x7, GCSPR_EL0
-// CHECK: msr     GCSPR_EL0, x6                   // encoding: [0x26,0x25,0x1b,0xd5]
-// CHECK: mrs     x7, GCSPR_EL0                   // encoding: [0x27,0x25,0x3b,0xd5]
+// CHECK-INST: mrs x7, GCSPR_EL0
+// CHECK-ENCODING: encoding: [0x27,0x25,0x3b,0xd5]
+// CHECK-UNKNOWN:  d53b2527 mrs x7, GCSPR_EL0
 
 msr GCSCR_EL2, x10
+// CHECK-INST: msr GCSCR_EL2, x10
+// CHECK-ENCODING: encoding: [0x0a,0x25,0x1c,0xd5]
+// CHECK-UNKNOWN:  d51c250a msr GCSCR_EL2, x10
+
 mrs x11, GCSCR_EL2
-// CHECK: msr     GCSCR_EL2, x10                  // encoding: [0x0a,0x25,0x1c,0xd5]
-// CHECK: mrs     x11, GCSCR_EL2                  // encoding: [0x0b,0x25,0x3c,0xd5]
+// CHECK-INST: mrs x11, GCSCR_EL2
+// CHECK-ENCODING: encoding: [0x0b,0x25,0x3c,0xd5]
+// CHECK-UNKNOWN:  d53c250b mrs x11, GCSCR_EL2
 
 msr GCSPR_EL2, x12
+// CHECK-INST: msr GCSPR_EL2, x12
+// CHECK-ENCODING: encoding: [0x2c,0x25,0x1c,0xd5]
+// CHECK-UNKNOWN:  d51c252c msr GCSPR_EL2, x12
+
 mrs x13, GCSPR_EL2
-// CHECK: msr     GCSPR_EL2, x12                  // encoding: [0x2c,0x25,0x1c,0xd5]
-// CHECK: mrs     x13, GCSPR_EL2                  // encoding: [0x2d,0x25,0x3c,0xd5]
+// CHECK-INST: mrs x13, GCSPR_EL2
+// CHECK-ENCODING: encoding: [0x2d,0x25,0x3c,0xd5]
+// CHECK-UNKNOWN:  d53c252d mrs x13, GCSPR_EL2
 
 msr GCSCR_EL12, x14
+// CHECK-INST: msr GCSCR_EL12, x14
+// CHECK-ENCODING: encoding: [0x0e,0x25,0x1d,0xd5]
+// CHECK-UNKNOWN:  d51d250e msr GCSCR_EL12, x14
+
 mrs x15, GCSCR_EL12
-// CHECK: msr     GCSCR_EL12, x14                 // encoding: [0x0e,0x25,0x1d,0xd5]
-// CHECK: mrs     x15, GCSCR_EL12                 // encoding: [0x0f,0x25,0x3d,0xd5]
+// CHECK-INST: mrs x15, GCSCR_EL12
+// CHECK-ENCODING: encoding: [0x0f,0x25,0x3d,0xd5]
+// CHECK-UNKNOWN:  d53d250f mrs x15, GCSCR_EL12
 
 msr GCSPR_EL12, x16
+// CHECK-INST: msr GCSPR_EL12, x16
+// CHECK-ENCODING: encoding: [0x30,0x25,0x1d,0xd5]
+// CHECK-UNKNOWN:  d51d2530 msr GCSPR_EL12, x16
+
 mrs x17, GCSPR_EL12
-// CHECK: msr     GCSPR_EL12, x16                 // encoding: [0x30,0x25,0x1d,0xd5]
-// CHECK: mrs     x17, GCSPR_EL12                 // encoding: [0x31,0x25,0x3d,0xd5]
+// CHECK-INST: mrs x17, GCSPR_EL12
+// CHECK-ENCODING: encoding: [0x31,0x25,0x3d,0xd5]
+// CHECK-UNKNOWN:  d53d2531 mrs x17, GCSPR_EL12
 
 msr GCSCR_EL3, x18
+// CHECK-INST: msr GCSCR_EL3, x18
+// CHECK-ENCODING: encoding: [0x12,0x25,0x1e,0xd5]
+// CHECK-UNKNOWN:  d51e2512 msr GCSCR_EL3, x18
+
 mrs x19, GCSCR_EL3
-// CHECK: msr     GCSCR_EL3, x18                  // encoding: [0x12,0x25,0x1e,0xd5]
-// CHECK: mrs     x19, GCSCR_EL3                  // encoding: [0x13,0x25,0x3e,0xd5]
+// CHECK-INST: mrs x19, GCSCR_EL3
+// CHECK-ENCODING: encoding: [0x13,0x25,0x3e,0xd5]
+// CHECK-UNKNOWN:  d53e2513 mrs x19, GCSCR_EL3
 
 msr GCSPR_EL3, x20
+// CHECK-INST: msr GCSPR_EL3, x20
+// CHECK-ENCODING: encoding: [0x34,0x25,0x1e,0xd5]
+// CHECK-UNKNOWN:  d51e2534 msr GCSPR_EL3, x20
+
 mrs x21, GCSPR_EL3
-// CHECK: msr     GCSPR_EL3, x20                  // encoding: [0x34,0x25,0x1e,0xd5]
-// CHECK: mrs     x21, GCSPR_EL3                  // encoding: [0x35,0x25,0x3e,0xd5]
+// CHECK-INST: mrs x21, GCSPR_EL3
+// CHECK-ENCODING: encoding: [0x35,0x25,0x3e,0...
[truncated]

This was referenced Jun 30, 2025
Open
Open
Open
tmatheson-arm
tmatheson-arm reviewed Jun 30, 2025
View reviewed changes
llvm/test/MC/AArch64/armv9.4a-gcs.s Outdated
Comment on lines 153 to 156
gcsb dsync
// CHECK: gcsb dsync // encoding: [0x7f,0x22,0x03,0xd5]
// ERROR-NO-GCS-NOT: [[@LINE-2]]:1: error: instruction requires: gcs
// NO-GCS: hint #19 // encoding: [0x7f,0x22,0x03,0xd5]
// CHECK-INST: gcsb dsync
// CHECK-ENCODING: encoding: [0x7f,0x22,0x03,0xd5]
// CHECK-UNKNOWN: d503227f hint #19
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Without +gcs this should disassemble to a clean hint #19, which was checked before but not now (CHECK-UNKNOWN is checking the output of llvm-objdump)

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thanks, good spot. I've re-added these back in as extra tests.

llvm/test/MC/AArch64/armv9.4a-lse128.s
// CHECK-ENCODING: encoding: [0x61,0x11,0x22,0x19]
// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128
// CHECK-UNKNOWN: 19221161 <unknown>
ldclrp x21, x22, [sp]
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

No spaces between cases?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thanks, now fixed.

llvm/test/MC/AArch64/armv9.2a-mec.s
// CHECK-INST: dc cipae, x0
// CHECK-ENCODING: encoding: [0x00,0x7e,0x0c,0xd5]
// CHECK-ERROR: :[[@LINE-3]]:4: error: DC CIPAE requires: mec
// CHECK-UNKNOWN: d50c7e00 sys #4, c7, c14, #0, x0
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

These are also missing the test that CHECK-NO-MEC was doing, that they disassemble to a clean sys without +mec.

We should probably also be checking that the sys instructions correctly assemble somewhere.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thanks, both fixed.

@jthackray jthackray force-pushed the users/jthackray/unify-tests1 branch from 0179782 to a788f61 Compare June 30, 2025 16:21
@jthackray jthackray force-pushed the users/jthackray/unify-tests2 branch from 40dca64 to 9b48b94 Compare June 30, 2025 16:22
@jthackray @virginia-cangelosi
[AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC)
69c9707 
This is a series of patches (2/4) to unify assembly/disassembly of
recent AArch64 tests into a single file. The aim is to improve
consistency, so that all instructions and system registers are
thoroughly tested, and future test cases will be in a unified format.

This patch:
 * removes .txt tests which have only one feature required
 * makes the .s tests have a roundabout run line to test both encoding and assembly
 * creates diagnostic tests when needed
 * fixes naming convention of tests

Co-authored-by: Virginia Cangelosi <[email protected]>
@jthackray jthackray changed the base branch from users/jthackray/unify-tests1 to main June 30, 2025 16:45
@jthackray jthackray changed the base branch from main to users/jthackray/unify-tests1 June 30, 2025 16:46
@jthackray @virginia-cangelosi
fixup! [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (…
17e13b2 
…NFC)

This is a series of patches (2/4) to unify assembly/disassembly of
recent AArch64 tests into a single file. The aim is to improve
consistency, so that all instructions and system registers are
thoroughly tested, and future test cases will be in a unified format.

This patch:
 * removes .txt tests which have only one feature required
 * makes the .s tests have a roundabout run line to test both encoding and assembly
 * creates diagnostic tests when needed
 * fixes naming convention of tests

Co-authored-by: Virginia Cangelosi <[email protected]>
@jthackray jthackray force-pushed the users/jthackray/unify-tests1 branch from a788f61 to 2808d3f Compare June 30, 2025 18:05
@jthackray jthackray force-pushed the users/jthackray/unify-tests2 branch from 9b48b94 to 17e13b2 Compare June 30, 2025 18:05
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@tmatheson-arm tmatheson-arm tmatheson-arm left review comments

@CarolineConcatto CarolineConcatto Awaiting requested review from CarolineConcatto

@kmclaughlin-arm kmclaughlin-arm Awaiting requested review from kmclaughlin-arm

@Lukacma Lukacma Awaiting requested review from Lukacma

@amilendra amilendra Awaiting requested review from amilendra

@virginia-cangelosi virginia-cangelosi Awaiting requested review from virginia-cangelosi

@rgwott rgwott Awaiting requested review from rgwott

@pratlucas pratlucas Awaiting requested review from pratlucas

Assignees
No one assigned
Labels
backend:AArch64 mc Machine (object) code
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
3 participants
@jthackray @llvmbot @tmatheson-arm