Skip to content

[LoongArch] Prevent R0/R1 allocation for rj operand of [G]CSRXCHG #140862

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
May 22, 2025
+44 −4
Merged

[LoongArch] Prevent R0/R1 allocation for rj operand of [G]CSRXCHG #140862

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
02bc62c
[LoongArch] Prevent R0/R1 allocation for rj operand of {G}CSRXCHG
heiher May 21, 2025
b7fbcf2
Address xen0n's comments
heiher May 22, 2025
cbd0f13
Replace {G}CSRXCHG with [G]CSRXCHG to align with LoongArch ISA Manual…
heiher May 22, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 3 additions & 0 deletions llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1633,6 +1633,9 @@ LoongArchAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
return Match_Success;
}

Copy link
Member

@MaskRay MaskRay May 23, 2025 •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

AsmParser and Disassembler changes require a llvm-mc -filetype=obj ... | llvm-objdump -dr test in llvm/test/MC/ . For this no-r0-no-r1 change we also need a negative test.

# RUN: not llvm-mc ... --defsym ERR=1

.ifdef ERR
.endif

Copy link
Member Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thanks! These are already covered:

llvm-project/llvm/test/MC/LoongArch/Basic/Privilege/valid.s

Lines 24 to 26 in 8d30c73

# CHECK-ASM-AND-OBJ: csrxchg $a2, $s4, 214
# CHECK-ASM: encoding: [0x66,0x5b,0x03,0x04]
csrxchg $a2, $s4, 214

llvm-project/llvm/test/MC/LoongArch/Basic/Privilege/invalid.s

Lines 4 to 8 in 8d30c73

## csrxchg: rj != 0,1
csrxchg $a0, $zero, 0
# ERR: :[[#@LINE-1]]:15: error: must not be $r0 or $r1
csrxchg $a0, $ra, 0
# ERR: :[[#@LINE-1]]:15: error: must not be $r0 or $r1

if (Kind == MCK_GPRNoR0R1 && (Reg == LoongArch::R0 || Reg == LoongArch::R1))
return Match_RequiresOpnd2NotR0R1;

return Match_InvalidOperand;
}

Expand Down
8 changes: 8 additions & 0 deletions llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -62,6 +62,14 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
return MCDisassembler::Success;
}

static DecodeStatus
DecodeGPRNoR0R1RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address,
const MCDisassembler *Decoder) {
if (RegNo <= 1)
return MCDisassembler::Fail;
return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
}

static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2431,7 +2431,7 @@ let hasSideEffects = 1, Constraints = "$rd = $dst" in {
def CSRWR : FmtCSR<0x04000020, (outs GPR:$dst),
(ins GPR:$rd, uimm14:$csr_num), "$rd, $csr_num">;
def CSRXCHG : FmtCSRXCHG<0x04000000, (outs GPR:$dst),
(ins GPR:$rd, GPR:$rj, uimm14:$csr_num),
(ins GPR:$rd, GPRNoR0R1:$rj, uimm14:$csr_num),
"$rd, $rj, $csr_num">;
} // hasSideEffects = 1, Constraints = "$rd = $dst"

Expand Down Expand Up @@ -2478,8 +2478,8 @@ def IDLE : MISC_I15<0x06488000>;
def : Pat<(loongarch_csrrd uimm14:$imm14), (CSRRD uimm14:$imm14)>;
def : Pat<(loongarch_csrwr GPR:$rd, uimm14:$imm14),
(CSRWR GPR:$rd, uimm14:$imm14)>;
def : Pat<(loongarch_csrxchg GPR:$rd, GPR:$rj, uimm14:$imm14),
(CSRXCHG GPR:$rd, GPR:$rj, uimm14:$imm14)>;
def : Pat<(loongarch_csrxchg GPR:$rd, GPRNoR0R1:$rj, uimm14:$imm14),
(CSRXCHG GPR:$rd, GPRNoR0R1:$rj, uimm14:$imm14)>;

def : Pat<(loongarch_iocsrrd_b GPR:$rj), (IOCSRRD_B GPR:$rj)>;
def : Pat<(loongarch_iocsrrd_h GPR:$rj), (IOCSRRD_H GPR:$rj)>;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/LoongArch/LoongArchLVZInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ let Constraints = "$rd = $dst" in {
def GCSRWR : FmtCSR<0x05000020, (outs GPR:$dst),
(ins GPR:$rd, uimm14:$csr_num), "$rd, $csr_num">;
def GCSRXCHG : FmtCSRXCHG<0x05000000, (outs GPR:$dst),
(ins GPR:$rd, GPR:$rj, uimm14:$csr_num),
(ins GPR:$rd, GPRNoR0R1:$rj, uimm14:$csr_num),
"$rd, $rj, $csr_num">;
} // Constraints = "$rd = $dst"

Expand Down
5 changes: 5 additions & 0 deletions llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -127,6 +127,11 @@ def GPRT : GPRRegisterClass<(add // a0...a7, t0...t8
// prediction.
def GPRJR : GPRRegisterClass<(sub GPR, R1)>;

// Don't use R0 or R1 for the rj operand of [G]CSRXCHG, because when rj is
// encoded as 0 or 1, the instruction is interpreted as [G]CSRRD or [G]CSRWR,
// respectively, rather than [G]CSRXCHG.
def GPRNoR0R1 : GPRRegisterClass<(sub GPR, R0, R1)>;

// Floating point registers

let RegAltNameIndices = [RegAliasName] in {
Expand Down
24 changes: 24 additions & 0 deletions llvm/test/CodeGen/LoongArch/csrxchg-intrinsic.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,24 @@
; RUN: llc --mtriple=loongarch32 --mattr=+f --verify-machineinstrs < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+f --verify-machineinstrs < %s | FileCheck %s

declare i32 @llvm.loongarch.csrxchg.w(i32, i32, i32 immarg)

;; Check that the rj operand of csrxchg is not R0.
define void @csrxchg_w_rj_not_r0(i32 signext %a) {
; CHECK-NOT: csrxchg ${{[a-z]*}}, $r0, 0
; CHECK-NOT: csrxchg ${{[a-z]*}}, $zero, 0
entry:
%0 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %a, i32 0, i32 0)
ret void
}

;; Check that the rj operand of csrxchg is not R1.
define i32 @csrxchg_w_rj_not_r1() {
; CHECK-NOT: csrxchg ${{[a-z]*}}, $r1, 0
; CHECK-NOT: csrxchg ${{[a-z]*}}, $ra, 0
entry:
%0 = tail call i32 asm "", "=r,r,i,{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r13},{r14},{r15},{r16},{r17},{r18},{r19},{r20},{r23},{r24},{r25},{r26},{r27},{r28},{r29},{r30},{r31},0"(i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%1 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %0, i32 4, i32 0)
%2 = tail call i32 asm "", "=r,r,i,{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r13},{r14},{r15},{r16},{r17},{r18},{r19},{r20},{r23},{r24},{r25},{r26},{r27},{r28},{r29},{r30},{r31},0"(i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 %1)
ret i32 %2
}
Loading