add stxvprl[l]

Author: lei137

llvm/lib/Target/PowerPC/PPCInstrFuture.td

@@ -94,7 +94,7 @@ def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB),
           (STXVRL $XT, $RA, $RB)>;
 def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB),
           (STXVRLL $XT, $RA, $RB)>;
-def : Pat<(int_ppc_vsx_stxvprl v256i1:$XT, addr:$RA, i64:$RB),
-          (STXVPRL $XT, $RA, $RB)>;
-def : Pat<(int_ppc_vsx_stxvprll v256i1:$XT, addr:$RA, i64:$RB),
-          (STXVPRLL $XT, $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvprl v256i1:$XTp, addr:$RA, i64:$RB),
+          (STXVPRL $XTp, $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB),
+          (STXVPRLL $XTp, $RA, $RB)>;

llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll

@@ -70,3 +70,31 @@ entry:
   ret void
 }
 declare void @llvm.ppc.vsx.stxvrll(<4 x i32>, ptr, i64)
+
+define void @testSTXVPRL(ptr %v, ptr %vp, i64 %len) {
+; CHECK-LABEL: testSTXVPRL:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxv v2
+; CHECK-NEXT:    lxv v3
+; CHECK-NEXT:    stxvprl vsp34, r4, r5
+; CHECK-NEXT:    blr
+entry:
+  %0 = load <256 x i1>, ptr %v, align 32
+  tail call void @llvm.ppc.vsx.stxvprl(<256 x i1> %0, ptr %vp, i64 %len)
+  ret void
+}
+declare void @llvm.ppc.vsx.stxvprl(<256 x i1>, ptr, i64)
+
+define void @testSTXVPRLL(ptr %v, ptr %vp, i64 %len) {
+; CHECK-LABEL: testSTXVPRLL:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxv v2
+; CHECK-NEXT:    lxv v3
+; CHECK-NEXT:    stxvprll vsp34, r4, r5
+; CHECK-NEXT:    blr
+entry:
+  %0 = load <256 x i1>, ptr %v, align 32
+  tail call void @llvm.ppc.vsx.stxvprll(<256 x i1> %0, ptr %vp, i64 %len)
+  ret void
+}
+declare void @llvm.ppc.vsx.stxvprll(<256 x i1>, ptr, i64)