add stxvprl[l]

Author: lei137

llvm/lib/Target/PowerPC/PPCInstrFuture.td

@@ -83,11 +83,18 @@ let Predicates = [HasVSX, IsISAFuture] in {
   }
 }
 
+// Load VSX Vector with Right Length Left-justified.
 def : Pat<(v4i32 (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)), (LXVRL $RA, $RB)>;
 def : Pat<(v4i32 (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)), (LXVRLL $RA, $RB)>;
 def : Pat<(v256i1 (int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
 def : Pat<(v256i1 (int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
-/*
-def : Pat<(int_ppc_vsx_stxvrl v256i1:$XT, addr:$RA, i64:$RB),
+
+// Store VSX Vector with Right Length Left-justified.
+def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB),
           (STXVRL $XT, $RA, $RB)>;
-*/
+def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB),
+          (STXVRLL $XT, $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvprl v256i1:$XT, addr:$RA, i64:$RB),
+          (STXVPRL $XT, $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvprll v256i1:$XT, addr:$RA, i64:$RB),
+          (STXVPRLL $XT, $RA, $RB)>;

llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll

@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
 ; RUN:   FileCheck %s
@@ -50,3 +49,24 @@ entry:
 }
 declare <256 x i1> @llvm.ppc.vsx.lxvprll(ptr, i64)
 
+define void @testSTXVRL(<4 x i32> %a, ptr %b, i64 %c) {
+; CHECK-LABEL: testSTXVRL:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stxvrl v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
+; CHECK:         blr
+entry:
+  tail call void @llvm.ppc.vsx.stxvrl(<4 x i32> %a, ptr %b, i64 %c)
+  ret void
+}
+declare void @llvm.ppc.vsx.stxvrl(<4 x i32>, ptr, i64)
+
+define void @testSTXVRLL(<4 x i32> %a, ptr %b, i64 %c) {
+; CHECK-LABEL: testSTXVRLL:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stxvrll v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
+; CHECK:         blr
+entry:
+  tail call void @llvm.ppc.vsx.stxvrll(<4 x i32> %a, ptr %b, i64 %c)
+  ret void
+}
+declare void @llvm.ppc.vsx.stxvrll(<4 x i32>, ptr, i64)