t480 port #1906

tlaurion · 2025-02-11T18:46:08Z

Disclaimer: This PR picks https://review.coreboot.org/c/coreboot/+/83274 and patches added by libreboot as coreboot 24.12 release commit as a base. Whatever is not fixed in WiP support of coreboot should be discussed on that patchset.

This PR should build, but is incomplete as of now. This PR is a draft permitting to review under this PR what needs to be changed to have complete t480 support.

It merges the prior work of @akunterkontrolle and @notgivenby and @gaspar-ilom from #1885 and #1907

From notes under #1885 (comment)

My total 30h contribution (and counting) for now is at https://github.com/tlaurion/heads/tree/poc_t480

Combines the three separated efforts:
- https://github.com/notgivenby/heads/tree/board_t480
https://github.com/akunterkontrolle/heads/tree/board_t480
https://github.com/gaspar-ilom/heads/tree/t480
signs commits with my key (co-authoring of commits)
fixes crossgcc fetch script to use libreboot mirror
fixes some coreboot config, theoritically working pr0 (to be tested)
fixes t480 board config to use ~~target/t480~~-> adapted https://github.com/gaspar-ilom/heads/tree/t480 work, which calls blobs scripts from targets/xx80_me_blobs.mk
~~fixes blob download script needing to call python directly (nix has environment paths, need to call python, cannot call python script directly)~~ : ‎blobs/xx80/download_clean_deguard_me.sh is used instead from @gaspar-ilom
CircleCI board addition so that we can point to build errors directly and reproducible builds for a specific commit
t480-maximized -> t480: those are not maximized boards; ME is not neutered nor freed spaced reused in coreboot BIOS region. TODO: revisit. A lot of modules are removed, bringing size of ME to 1.1mb?
As of now firewire blob from @notgivenby is not injected in firmware anymore. Do we really want/need it? why?
- review of coreboot configs need review
TPM2 toolstack added in board configs in recent commit (was based on t440p wich is tpm1, missed that, prior, sorry).

TODO:

@gaspar-ilom @notgivenby @akunterkontrolle : test test test and report.
review and comment through https://github.com/linuxboot/heads/pull/1906/files
revisit decision of board names: ME is neutered still reducing size of ME to 1.1mb. This is maximized boards, if we move freed space of ME region to BIOS region in IFD, that is.
Add board testers under BOARD_TESTERS.md, only @gaspar-ilom is there for now.
review if we want to reuse all libreboot patches or select which ones we want to keep in tree
testing from board owners, iterate in commits that are signed and can be cherry-picked from other contributors branches
re-add thunderbolt firmware preparation, document in board config by referring to libreboot docs.
merge

Signed-off-by: Thierry Laurion <[email protected]>

…for t480 Signed-off-by: Thierry Laurion <[email protected]>

Signed-off-by: Thierry Laurion <[email protected]>

…ce its not sharing the same coreboot buildstack (something 25.X.X, need to check) Signed-off-by: Thierry Laurion <[email protected]>

…ack, since its not sharing the same coreboot buildstack (something 25.X.X, need to check)" This reverts commit b1f279354388fd8e71abd9f1514246d7e9f6ed1c. Hmmm.... WGET="" bin/fetch_coreboot_crossgcc_archive.sh "/home/user/heads/build/x86/coreboot-t480" "binutils" "/home/user/heads/packages/x86" --2025-02-11 14:46:38-- https://ftpmirror.gnu.org/binutils/binutils-2.43.1.tar.xz Resolving ftpmirror.gnu.org (ftpmirror.gnu.org)... 209.51.188.200, 2001:470:142:5::200 Connecting to ftpmirror.gnu.org (ftpmirror.gnu.org)|209.51.188.200|:443... connected. HTTP request sent, awaiting response... 302 Moved Temporarily Location: https://mirror.csclub.uwaterloo.ca/gnu/binutils/binutils-2.43.1.tar.xz [following] --2025-02-11 14:46:40-- https://mirror.csclub.uwaterloo.ca/gnu/binutils/binutils-2.43.1.tar.xz Resolving mirror.csclub.uwaterloo.ca (mirror.csclub.uwaterloo.ca)... 129.97.134.71, 2620:101:f000:4901:c5c:0:f:1055 Connecting to mirror.csclub.uwaterloo.ca (mirror.csclub.uwaterloo.ca)|129.97.134.71|:443... connected. HTTP request sent, awaiting response... 200 OK Length: 28174300 (27M) [text/plain] Saving to: '/home/user/heads/packages/x86/coreboot-crossgcc-binutils-2.43.1.tar.xz.tmp' /home/user/heads/packages/x86/coreboot-crossgcc-binu 100%[=====================================================================================================================>] 26.87M 8.88MB/s in 3.0s 2025-02-11 14:46:44 (8.88 MB/s) - '/home/user/heads/packages/x86/coreboot-crossgcc-binutils-2.43.1.tar.xz.tmp' saved [28174300/28174300] /home/user/heads/packages/x86/coreboot-crossgcc-binutils-2.43.1.tar.xz.tmp: OK touch "/home/user/heads/build/x86/coreboot-t480/.heads-crossgcc-pkg-binutils" WGET="" bin/fetch_coreboot_crossgcc_archive.sh "/home/user/heads/build/x86/coreboot-t480" "gcc" "/home/user/heads/packages/x86" --2025-02-11 14:46:44-- https://ftpmirror.gnu.org/gcc/gcc-14.2.0/gcc-14.2.0.tar.xz Resolving ftpmirror.gnu.org (ftpmirror.gnu.org)... 209.51.188.200, 2001:470:142:5::200 Connecting to ftpmirror.gnu.org (ftpmirror.gnu.org)|209.51.188.200|:443... connected. HTTP request sent, awaiting response... 302 Moved Temporarily Location: https://mirror2.evolution-host.com/gnu/gcc/gcc-14.2.0/gcc-14.2.0.tar.xz [following] --2025-02-11 14:46:44-- https://mirror2.evolution-host.com/gnu/gcc/gcc-14.2.0/gcc-14.2.0.tar.xz Resolving mirror2.evolution-host.com (mirror2.evolution-host.com)... 167.114.8.249, 2607:5300:60:450d:c259:13f4:6df0:1 Connecting to mirror2.evolution-host.com (mirror2.evolution-host.com)|167.114.8.249|:443... connected. HTTP request sent, awaiting response... 200 OK Length: 92306460 (88M) [application/x-xz] Saving to: '/home/user/heads/packages/x86/coreboot-crossgcc-gcc-14.2.0.tar.xz.tmp' /home/user/heads/packages/x86/coreboot-crossgcc-gcc- 100%[=====================================================================================================================>] 88.03M 32.9MB/s in 2.7s 2025-02-11 14:46:48 (32.9 MB/s) - '/home/user/heads/packages/x86/coreboot-crossgcc-gcc-14.2.0.tar.xz.tmp' saved [92306460/92306460] /home/user/heads/packages/x86/coreboot-crossgcc-gcc-14.2.0.tar.xz.tmp: OK touch "/home/user/heads/build/x86/coreboot-t480/.heads-crossgcc-pkg-gcc" WGET="" bin/fetch_coreboot_crossgcc_archive.sh "/home/user/heads/build/x86/coreboot-t480" "nasm" "/home/user/heads/packages/x86" --2025-02-11 14:46:48-- https://www.nasm.us/pub/nasm/releasebuilds/2.16.03/nasm-2.16.03.tar.bz2 Resolving www.nasm.us (www.nasm.us)... 198.137.202.136, 2607:7c80:54:3::136 Connecting to www.nasm.us (www.nasm.us)|198.137.202.136|:443... connected. HTTP request sent, awaiting response... 200 OK Length: 1361988 (1.3M) [application/x-bzip2] Saving to: '/home/user/heads/packages/x86/coreboot-crossgcc-nasm-2.16.03.tar.bz2.tmp' /home/user/heads/packages/x86/coreboot-crossgcc-nasm 100%[=====================================================================================================================>] 1.30M 2.90MB/s in 0.4s 2025-02-11 14:46:49 (2.90 MB/s) - '/home/user/heads/packages/x86/coreboot-crossgcc-nasm-2.16.03.tar.bz2.tmp' saved [1361988/1361988] /home/user/heads/packages/x86/coreboot-crossgcc-nasm-2.16.03.tar.bz2.tmp: OK touch "/home/user/heads/build/x86/coreboot-t480/.heads-crossgcc-pkg-nasm" WGET="" bin/fetch_coreboot_crossgcc_archive.sh "/home/user/heads/build/x86/coreboot-t480" "iasl" "/home/user/heads/packages/x86" --2025-02-11 14:46:49-- https://distfiles.macports.org/acpica/acpica-unix-20241212.tar.gz Resolving distfiles.macports.org (distfiles.macports.org)... 151.101.138.132 Connecting to distfiles.macports.org (distfiles.macports.org)|151.101.138.132|:443... connected. HTTP request sent, awaiting response... 404 Not Found 2025-02-11 14:46:50 ERROR 404: Not Found. Failed to download https://distfiles.macports.org/acpica/acpica-unix-20241212.tar.gz Try mirrors for coreboot-crossgcc-acpica-unix-20241212.tar.gz --2025-02-11 14:46:50-- https://storage.puri.st/heads-packages/coreboot-crossgcc-acpica-unix-20241212.tar.gz Resolving storage.puri.st (storage.puri.st)... 146.190.140.226 Connecting to storage.puri.st (storage.puri.st)|146.190.140.226|:443... connected. HTTP request sent, awaiting response... 404 Not Found 2025-02-11 14:46:51 ERROR 404: Not Found. Failed to download https://storage.puri.st/heads-packages/coreboot-crossgcc-acpica-unix-20241212.tar.gz --2025-02-11 14:46:51-- https://storage.puri.sm/heads-packages/coreboot-crossgcc-acpica-unix-20241212.tar.gz Resolving storage.puri.sm (storage.puri.sm)... 146.190.140.226 Connecting to storage.puri.sm (storage.puri.sm)|146.190.140.226|:443... connected. HTTP request sent, awaiting response... 404 Not Found 2025-02-11 14:46:52 ERROR 404: Not Found. Failed to download https://storage.puri.sm/heads-packages/coreboot-crossgcc-acpica-unix-20241212.tar.gz Signed-off-by: Thierry Laurion <[email protected]>

…hon when used under nix docker Signed-off-by: Thierry Laurion <[email protected]>

…ls blobs scripts Signed-off-by: Thierry Laurion <[email protected]>

… as base Signed-off-by: Thierry Laurion <[email protected]>

…onfig and config/coreboot-novacustom-nv4x_adl.config Then saved back in oldconfig with ./docker_repro.sh make BOARD=t480-maximized coreboot.modify_and_save_oldconfig_in_place Notes: - Pr0 requirements don't stick, investigate - real quick overview of config, just rying to get thing build here Signed-off-by: Thierry Laurion <[email protected]>

…EURL to use one of libreboot web mirror Signed-off-by: Thierry Laurion <[email protected]>

…ot 24.02 buildstack) Signed-off-by: Thierry Laurion <[email protected]>

…les in tree as per http://web.archive.org/web/20250211155526/https://notgivenby.github.io/heads-wiki/t480-port/#coreboot-config-for-t480 : No joy building, but will dump progress for others to pickup Signed-off-by: Thierry Laurion <[email protected]>

…ake first layer Will fail at Updating git submodules. payloads/external/Makefile.mk:399: "Using host toolchain to build Linuxboot" GEN build.h IFDTOOL -p sklkbl -F t480-maximized/fmap-template.fmd ../../../blobs/t480/ifd_16 HOSTCC cbfstool/fmd_parser.o HOSTCC cbfstool/fmd_scanner.o make[1]: *** No rule to make target '../../../vendorfiles/kabylake/Fsp_M.fd', needed by 't480-maximized/coreboot.pre'. Stop. make[1]: *** Waiting for unfinished jobs.... File ../../../blobs/t480/ifd_16 is 4096 bytes Wrote layout to t480-maximized/fmap-template.fmd Signed-off-by: Thierry Laurion <[email protected]>

…iles exist For repro: - To remove all files created by patches (would error to help dev remove them manually) - echo "bogus" | tee build/x86/coreboot-t480/.canary - sudo rm -rf build/x86/coreboot-t480/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480* - sudo rm build/x86/libgpg-error-1.46/src/syscfg/lock-obj-pub.powerpc64le-unknown-linux-musl.h - Remove all .canary files, outside of detected git forks to speedup local builds, rebuilding only new files with make magic - ./docker_repro.sh make BOARD=t480-maximized real.remove_canary_files-extract_patch_rebuild_what_changed - Rebuild from sources: unpack archives/git clone, patch, build from source - ./docker_repro.sh make BOARD=t480-maximized Signed-off-by: Thierry Laurion <[email protected]>

…ream PR0 patchset https://review.coreboot.org/c/coreboot/+/85278 Repro: git fetch https://review.coreboot.org/coreboot refs/changes/78/85278/3 && git format-patch -1 --stdout FETCH_HEAD > patches/coreboot-t480/85278-post-skylake-pr0.patch Unfortunately Applying patch file : patches/coreboot-t480/85278-post-skylake-pr0.patch Checking patch build/x86/coreboot-t480/src/soc/intel/alderlake/finalize.c... Checking patch build/x86/coreboot-t480/src/soc/intel/cannonlake/finalize.c... Checking patch build/x86/coreboot-t480/src/soc/intel/common/block/lpc/Makefile.mk... Checking patch build/x86/coreboot-t480/src/soc/intel/common/block/smm/smihandler.c... Checking patch build/x86/coreboot-t480/src/soc/intel/common/pch/include/intelpch/lockdown.h... Checking patch build/x86/coreboot-t480/src/soc/intel/common/pch/lockdown/Kconfig... Checking patch build/x86/coreboot-t480/src/soc/intel/common/pch/lockdown/Makefile.mk... Checking patch build/x86/coreboot-t480/src/soc/intel/common/pch/lockdown/lockdown.c... Checking patch build/x86/coreboot-t480/src/soc/intel/common/pch/lockdown/lockdown_lpc.c... Checking patch build/x86/coreboot-t480/src/soc/intel/common/pch/lockdown/lockdown_spi.c... Checking patch build/x86/coreboot-t480/src/soc/intel/denverton_ns/lpc.c... Checking patch build/x86/coreboot-t480/src/soc/intel/elkhartlake/finalize.c... Checking patch build/x86/coreboot-t480/src/soc/intel/jasperlake/finalize.c... Checking patch build/x86/coreboot-t480/src/soc/intel/meteorlake/finalize.c... Checking patch build/x86/coreboot-t480/src/soc/intel/pantherlake/finalize.c... Checking patch build/x86/coreboot-t480/src/soc/intel/skylake/finalize.c... Checking patch build/x86/coreboot-t480/src/soc/intel/tigerlake/finalize.c... Checking patch build/x86/coreboot-t480/src/soc/intel/xeon_sp/finalize.c... Checking patch build/x86/coreboot-t480/src/soc/intel/xeon_sp/lockdown.c... error: while searching for: static void lpc_lockdown_config(void) { /* Set BIOS Interface Lock, BIOS Lock */ lpc_set_bios_interface_lock_down(); /* Only allow writes in SMM */ if (CONFIG(BOOTMEDIA_SMM_BWP)) { lpc_set_eiss(); lpc_enable_wp(); } lpc_set_lock_enable(); } void soc_lockdown_config(int chipset_lockdown) { if (chipset_lockdown == CHIPSET_LOCKDOWN_FSP) return; lpc_lockdown_config(); pmc_lockdown_config(); sata_lockdown_config(chipset_lockdown); spi_lockdown_config(chipset_lockdown); error: patch failed: build/x86/coreboot-t480/src/soc/intel/xeon_sp/lockdown.c:6 Applied patch build/x86/coreboot-t480/src/soc/intel/alderlake/finalize.c cleanly. Applied patch build/x86/coreboot-t480/src/soc/intel/cannonlake/finalize.c cleanly. Applied patch build/x86/coreboot-t480/src/soc/intel/common/block/lpc/Makefile.mk cleanly. Applied patch build/x86/coreboot-t480/src/soc/intel/common/block/smm/smihandler.c cleanly. Applied patch build/x86/coreboot-t480/src/soc/intel/common/pch/include/intelpch/lockdown.h cleanly. Applied patch build/x86/coreboot-t480/src/soc/intel/common/pch/lockdown/Kconfig cleanly. Applied patch build/x86/coreboot-t480/src/soc/intel/common/pch/lockdown/Makefile.mk cleanly. Applied patch build/x86/coreboot-t480/src/soc/intel/common/pch/lockdown/lockdown.c cleanly. Applied patch build/x86/coreboot-t480/src/soc/intel/common/pch/lockdown/lockdown_lpc.c cleanly. Applied patch build/x86/coreboot-t480/src/soc/intel/common/pch/lockdown/lockdown_spi.c cleanly. Applied patch build/x86/coreboot-t480/src/soc/intel/denverton_ns/lpc.c cleanly. Applied patch build/x86/coreboot-t480/src/soc/intel/elkhartlake/finalize.c cleanly. Applied patch build/x86/coreboot-t480/src/soc/intel/jasperlake/finalize.c cleanly. Applied patch build/x86/coreboot-t480/src/soc/intel/meteorlake/finalize.c cleanly. Applied patch build/x86/coreboot-t480/src/soc/intel/pantherlake/finalize.c cleanly. Applied patch build/x86/coreboot-t480/src/soc/intel/skylake/finalize.c cleanly. Applied patch build/x86/coreboot-t480/src/soc/intel/tigerlake/finalize.c cleanly. Applied patch build/x86/coreboot-t480/src/soc/intel/xeon_sp/finalize.c cleanly. Applying patch build/x86/coreboot-t480/src/soc/intel/xeon_sp/lockdown.c with 1 reject... Rejected hunk #1. make: *** [Makefile:570: /home/user/heads/build/x86/coreboot-t480/.canary] Error 1 Will have to edit patch Signed-off-by: Thierry Laurion <[email protected]>

…we are not interested into which are conflicting against coreboot upstream commit 2f1e4e5e8515dd350cc9d68b48d32a5b6b02ae6a Signed-off-by: Thierry Laurion <[email protected]>

…config Signed-off-by: Thierry Laurion <[email protected]>

…herwise build error Signed-off-by: Thierry Laurion <[email protected]>

tlaurion · 2025-02-11T22:13:33Z

002d107 adds PR0 (to be tested) and fix build issues.

time spent total 3h

… after kexec call to final OS. Otherwise, problem with coreboot config) Signed-off-by: Thierry Laurion <[email protected]>

notgivenby · 2025-02-11T23:54:53Z

@tlaurion please delete p from the folder name /boards/t480p-hotp-maximized . It should read t480-hotp-maximized. I believe the "p" was left from t440p.

Signed-off-by: gaspar-ilom <[email protected]>

…d error Signed-off-by: Thierry Laurion <[email protected]>

tlaurion · 2025-03-03T17:50:00Z

I successfully externally flashed my T480 (main chip and Thunderbolt) with the binary blobs from CircleCI @ tlaurion@438a061 !

For reference, used the artifacts from https://app.circleci.com/pipelines/github/tlaurion/heads/3191/workflows/d1e842f2-3cad-439c-9be9-611f4a4d4b52/jobs/64345/artifacts

So this shows that current PR is in good state ( tlaurion@438a061 is latest commit of this PR at this state)

You flashed tb or not?

tlaurion · 2025-03-03T17:50:18Z

730fdd1 removes t480 from CircleCI and moves boards to unmaintained until #1906 (and upstream https://review.coreboot.org/c/coreboot/+/83274) handles thermal control for all thinkpads correctly.

https://review.coreboot.org/c/coreboot/+/83274 will never be merged in its current state.
@notgivenby you should add link to your picture at https://review.coreboot.org/c/coreboot/+/83274 stating that if the line you referred is uncommented back (required for all other thinkpads) then t480 gets a brick.

Sorry folks, we won't merge t480 under master. This PR shows as of now that we could bump to 2412 though for all other boards that were currently based on 24.02.01, and that t480 code needs work to be part on next coreboot release.

Originally posted by @tlaurion in #1908 (comment)

rafaelsgirao · 2025-03-03T17:52:15Z

I successfully externally flashed my T480 (main chip and Thunderbolt) with the binary blobs from CircleCI @ tlaurion@438a061 !
For reference, used the artifacts from https://app.circleci.com/pipelines/github/tlaurion/heads/3191/workflows/d1e842f2-3cad-439c-9be9-611f4a4d4b52/jobs/64345/artifacts

So this shows that current PR is in good state. You flashed tb or not?

Yes, I did flash tb.bin from that same commit (and to add to the "to erase TB chip first or not" - my flasher initially states that it erases the chip before writing.)

MattClifton76 · 2025-03-03T17:53:44Z

Than I completely misunderstood you @MattClifton76 I thought your machine does not boot too. @tlaurion I can copy the file zip file (downloaded from CircleCI) if needed. So the hash integrity’s should have been checked…

I technically see the heads splash screen and then it's flashes some thermal warning text and shuts off.

UPDATE: I just flashed g438a061, didn't not flash the TB file yet. Was able to boot the computer back up.

MattClifton76 · 2025-03-03T17:58:25Z

Than I completely misunderstood you @MattClifton76 I thought your machine does not boot too. @tlaurion I can copy the file zip file (downloaded from CircleCI) if needed. So the hash integrity’s should have been checked…

@notgivenby So it was internally flashed from

@notgivenby is https://output.circle-artifacts.com/output/job/db932a2b-59b1-40bc-b61e-f27c799f71c4/artifacts/0/build/x86/t480-hotp-maximized/heads-t480-hotp-maximized-v0.2.0-2693-gc7d40ea.zip the file you flashed?

?

I did an internal flash with that build. Saw heads Splash screen and the thermal warning text for 1/2 a second then it shut off.

notgivenby · 2025-03-03T17:59:39Z

@rafaelsgirao Congrats!

"to erase TB chip first or not"

But you did not erase the TB first correct? Did you first flash the Heads and then tb.bin or other way around? Did you use flashrom?

notgivenby · 2025-03-03T18:07:57Z

I did an internal flash with that build. Saw heads Splash screen and the thermal warning text for 1/2 a second then it shut off.

@MattClifton76 The board is bricked. You can externally flash last commit tlaurion@438a061
This should help you. Please report.

tlaurion · 2025-03-03T18:15:46Z

I

removed t480 from Coreboot version bump 24.02.01 -> 24.12 for most board + Thinkpad T480 addition (coreboot upstream in WiP state) #1908, moving board under that PR to unmaintained.
created coreboot 24.12 bump with libreboot patchset (no thermal.asl commented per patch) to see all bumped boards fail compilation in CircleCI #1920 so that CircleCI pipeline will fail for all thinpad boards, so that can be reported
The pipeline failing for coreboot 24.12 bump with libreboot patchset (no thermal.asl commented per patch) to see all bumped boards fail compilation in CircleCI #1920 should be reported under https://review.coreboot.org/c/coreboot/+/83274, also posting @notgivenby image showing thermal issue report and auto-reboot, causing a brick

rafaelsgirao · 2025-03-03T18:17:33Z

@rafaelsgirao Congrats!

"to erase TB chip first or not"

But you did not erase the TB first correct? Did you first flash the Heads and then tb.bin or other way around? Did you use flashrom?

Thanks! First time flashing, glad it was a success.

I flashed with a Flipper Zero (using SPI Mem Manager app).

According to what's shown on screen, the Flipper automatically erases the the chip first before starting to write (and then verifies the image was written correctly).

notgivenby · 2025-03-03T18:26:52Z

also posting @notgivenby image showing

Done

MattClifton76 · 2025-03-03T19:40:57Z

I did an internal flash with that build. Saw heads Splash screen and the thermal warning text for 1/2 a second then it shut off.

@MattClifton76 The board is bricked. You can externally flash last commit tlaurion@438a061 This should help you. Please report.

I figured it was bricked, the Flash was successful, computer boots fine. Checking TB hashes at the moment

gaspar-ilom · 2025-03-03T23:11:32Z

@rafaelsgirao Congrats!

"to erase TB chip first or not"

But you did not erase the TB first correct? Did you first flash the Heads and then tb.bin or other way around? Did you use flashrom?

Thanks! First time flashing, glad it was a success.

I flashed with a Flipper Zero (using SPI Mem Manager app).

According to what's shown on screen, the Flipper automatically erases the the chip first before starting to write (and then verifies the image was written correctly).

@rafaelsgirao You have flashed both chips right? In which order? And can you actually confirm that your USB-C ports are working, not just charging but also data? Please test both of them.

@tlaurion I do believe that some parts of voodoo dance matter. After all my USB-C ports did not come back to live when re-flashing the original firmware which I had read with the programmer. I did that with both heads and the Lenovo bios. No luck. It is possible that there is some issue with my read. I did multiple consistent reads, though and one USB-C port was working before. So it is unlikely that just flashing the new tb.bin alone could have fixed it.

TL;DR Someone need to test it. Sorry, I am only moderately motivated to brick my USB ports again, especially because the voodoo dance takes a fair amount of time.

MattClifton76 · 2025-03-03T23:32:28Z

@rafaelsgirao Congrats!

"to erase TB chip first or not"

But you did not erase the TB first correct? Did you first flash the Heads and then tb.bin or other way around? Did you use flashrom?

Thanks! First time flashing, glad it was a success.

I flashed with a Flipper Zero (using SPI Mem Manager app).

According to what's shown on screen, the Flipper automatically erases the the chip first before starting to write (and then verifies the image was written correctly).

@rafaelsgirao You have flashed both chips right? In which order? And can you actually confirm that your USB-C ports are working, not just charging but also data? Please test both of them.

@tlaurion I do believe that some parts of voodoo dance matter. After all my USB-C ports did not come back to live when re-flashing the original firmware which I had read with the programmer. I did that with both heads and the Lenovo bios. No luck. It is possible that there is some issue with my read. I did multiple consistent reads, though and one USB-C port was working before. So it is unlikely that just flashing the new tb.bin alone could have fixed it.

TL;DR Someone need to test it. Sorry, I am only moderately motivated to brick my USB ports again, especially because the voodoo dance takes a fair amount of time.

I am back on Lenovo firmware 1.52, EC 1.22, TB 23. I have reflashed everything that I can. The Charge port USBc charges and recognizes drives, the other one to the right does not recognize my apricorn external hard drive, but it does recognize my nitrokey this was confirmed with the nitrokey app. I will add screenshots.

gaspar-ilom · 2025-03-04T10:19:21Z

I am back on Lenovo firmware 1.52, EC 1.22, TB 23. I have reflashed everything that I can. The Charge port USBc charges and recognizes drives, the other one to the right does not recognize my apricorn external hard drive, but it does recognize my nitrokey this was confirmed with the nitrokey app. I will add screenshots.

Have you just reflashed the tb.bin blob from this repository or your original read?

If not done yet it would be nice if you could flash heads first and then the tb.bin blob from this PR without doing any steps of the dance. Just to confirm that the dance is not necessary in case the Thunderbolt port is not yet broken by the bug.

Anyway, in order to properly confirm whether the dance is necessary we would need a board where the bug has already rendered Thunderbolt unusable and then try fixing it without any voodoo dance, ideally with heads already on the main SPI. We might have a hard time finding such boards, though...

EDIT: I will also report the issues with the second USB-C port upstream. I do not believe they are aware of the details?!

MattClifton76 · 2025-03-04T11:59:14Z

I am back on Lenovo firmware 1.52, EC 1.22, TB 23. I have reflashed everything that I can. The Charge port USBc charges and recognizes drives, the other one to the right does not recognize my apricorn external hard drive, but it does recognize my nitrokey this was confirmed with the nitrokey app. I will add screenshots.

Have you just reflashed the tb.bin blob from this repository or your original read?

If not done yet it would be nice if you could flash heads first and then the tb.bin blob from this PR without doing any steps of the dance. Just to confirm that the dance is not necessary in case the Thunderbolt port is not yet broken by the bug.

Anyway, in order to properly confirm whether the dance is necessary we would need a board where the bug has already rendered Thunderbolt unusable and then try fixing it without any voodoo dance, ideally with heads already on the main SPI. We might have a hard time finding such boards, though...

EDIT: I will also report the issues with the second USB-C port upstream. I do not believe they are aware of the details?!

i reflashed everything with fwupd program.

Break it down like crayola for me, where do i get the TB.bin blob from for heads? i just assumed i never needed to do that part since i was already on v23 with working ports, that assumption was based off libreboot docs. I read those while i still had windows installed and updated/downgraded what i needed to there.

rafaelsgirao · 2025-03-04T12:39:14Z

@rafaelsgirao Congrats!

"to erase TB chip first or not"

But you did not erase the TB first correct? Did you first flash the Heads and then tb.bin or other way around? Did you use flashrom?

Thanks! First time flashing, glad it was a success.
I flashed with a Flipper Zero (using SPI Mem Manager app).
According to what's shown on screen, the Flipper automatically erases the the chip first before starting to write (and then verifies the image was written correctly).

@rafaelsgirao You have flashed both chips right? In which order? And can you actually confirm that your USB-C ports are working, not just charging but also data? Please test both of them.

@tlaurion I do believe that some parts of voodoo dance matter. After all my USB-C ports did not come back to live when re-flashing the original firmware which I had read with the programmer. I did that with both heads and the Lenovo bios. No luck. It is possible that there is some issue with my read. I did multiple consistent reads, though and one USB-C port was working before. So it is unlikely that just flashing the new tb.bin alone could have fixed it.

TL;DR Someone need to test it. Sorry, I am only moderately motivated to brick my USB ports again, especially because the voodoo dance takes a fair amount of time.

Yes, I flashed both. First the Thunderbolt chip, then bios.

Afterwards I re-flashed my original bios read but left the Thunderbolt one flashed with tb.in and it also works just fine.

I also tested plugging in a USB-C monitor and it worked in all cases. Not entirely sure if that's equivalent to Thunderbolt chip working, though.

tlaurion · 2025-03-04T15:53:18Z

also posting @notgivenby image showing

Done

@notgivenby unfortunately, url doesn't show your picture under https://review.coreboot.org/c/coreboot/+/83274/25/src/ec/lenovo/h8/acpi/ec.asl#b334

-> https://private-user-images.githubusercontent.com/188742761/418507212-9315e896-514c-4d1d-b770-fa2fe998e198.jpeg?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3NDEwMjYzOTgsIm5iZiI6MTc0MTAyNjA5OCwicGF0aCI6Ii8xODg3NDI3NjEvNDE4NTA3MjEyLTkzMTVlODk2LTUxNGMtNGQxZC1iNzcwLWZhMmZlOTk4ZTE5OC5qcGVnP1gtQW16LUFsZ29yaXRobT1BV1M0LUhNQUMtU0hBMjU2JlgtQW16LUNyZWRlbnRpYWw9QUtJQVZDT0RZTFNBNTNQUUs0WkElMkYyMDI1MDMwMyUyRnVzLWVhc3QtMSUyRnMzJTJGYXdzNF9yZXF1ZXN0JlgtQW16LURhdGU9MjAyNTAzMDNUMTgyMTM4WiZYLUFtei1FeHBpcmVzPTMwMCZYLUFtei1TaWduYXR1cmU9YmE0ZGQwZDg0NjQyZDYxYzZkMTQ5Mjk1ZTlhYjgyNjY4NGNjNGNmMzlmOGMzZGU2OGE5ZjUxMGJhOGFkMTQ2MCZYLUFtei1TaWduZWRIZWFkZXJzPWhvc3QifQ.F3Hfo65rVdaJrU66sQtqsVIikxHii7wUC8GuCTawogg

should be
->

also posting @notgivenby image showing

Done

@notgivenby unfortunately, image doesn't resolve.
https://review.coreboot.org/c/coreboot/+/83274/25/src/ec/lenovo/h8/acpi/ec.asl#b334

Should point to #1908 (comment)

notgivenby · 2025-03-04T16:05:35Z

Should point to #1908 (comment)

@tlaurion Oh…Sorry…my bad. Corrected.

notgivenby · 2025-03-06T13:50:49Z

@gaspar-ilom My machine is on again. Do you still need original tb.bin?

gaspar-ilom · 2025-03-06T16:53:30Z

@gaspar-ilom My machine is on again. Do you still need original tb.bin?

No thanks. As mentioned I have already recovered by flashing the tb.bin blob from libreboot after doing the voodoo dance.

gaspar-ilom · 2025-03-06T16:55:58Z

Yes, I flashed both. First the Thunderbolt chip, then bios.

Afterwards I re-flashed my original bios read but left the Thunderbolt one flashed with tb.in and it also works just fine.

I also tested plugging in a USB-C monitor and it worked in all cases. Not entirely sure if that's equivalent to Thunderbolt chip working, though.

Looks like the current tb.bin blob works without a voodoo dance and even with coreboot already flashed. @rafaelsgirao or did you reboot after flashing tb.bin and before flashing heads?

rafaelsgirao · 2025-03-06T17:00:24Z

Looks like the current tb.bin blob works without a voodoo dance and even with coreboot already flashed. @rafaelsgirao or did you reboot after flashing tb.bin and before flashing heads?

I didn't boot between flashing Thunderbolt chip and flashing bios chip

gaspar-ilom · 2025-03-06T17:10:17Z

Break it down like crayola for me, where do i get the TB.bin blob from for heads? i just assumed i never needed to do that part since i was already on v23 with working ports, that assumption was based off libreboot docs. I read those while i still had windows installed and updated/downgraded what i needed to there.

@MattClifton76 You can find the tb.bin blob in circleci. This blob can be flashed externally. If you are willing to help with testing it would be great if you flash it externally (this is a different SPI chip) while heads is on the main SPI chip.

gaspar-ilom · 2025-03-06T17:13:54Z

Looks like the current tb.bin blob works without a voodoo dance and even with coreboot already flashed. @rafaelsgirao or did you reboot after flashing tb.bin and before flashing heads?

I didn't boot between flashing Thunderbolt chip and flashing bios chip

@rafaelsgirao Great and thanks for the feedback. Seems like no dancing needed.

@tlaurion It would be great though to confirm that this is the same for someone with a Thunderbolt chip where the bug has already kicked in. Anyway, for the time being I would consider it safe to just flash both chips at the same time without any voodoo dance. Can you update the documentation accordingly @notgivenby ? Or are there any concerns?

tlaurion · 2025-03-08T04:31:06Z

@gaspar-ilom your changes conficts with coreboot config for v540tu when attemping to merge your latest pr and i'm getting tired. Testing of both t480 and other thinkpads should continue under #1908 at this point, i'm tited of the duplicated effort. At this point if this PR worksm issue to be resolved is making sure there is no regression if all board that were 24.02.01 are now 24.12 as for t480 under #1908

Pr associated work on my side bumped from OP 20h to 30h with all cat hurdling, social media related work and upstream (libreboot) aborted collaboration, Editing OP

gaspar-ilom · 2025-03-08T21:01:30Z

@gaspar-ilom your changes conficts with coreboot config for v540tu when attemping to merge your latest pr and i'm getting tired. Testing of both t480 and other thinkpads should continue under #1908 at this point, i'm tited of the duplicated effort. At this point if this PR worksm issue to be resolved is making sure there is no regression if all board that were 24.02.01 are now 24.12 as for t480 under #1908

Lets close this PR then in favor of #1908

gaspar-ilom

Barring the missing patch to make the code work with other thinkpads I believe it can be merged as part of #1908

tlaurion · 2025-03-09T18:55:51Z

Superseded by #1908

akunterkontrolle and others added 18 commits February 11, 2025 11:25

Add additional coreboot version for T480

bce1881

Signed-off-by: Thierry Laurion <[email protected]>

Add coreboot patches for T480

ca1bd20

Signed-off-by: Thierry Laurion <[email protected]>

Add coreboot config for T480

b101d31

Signed-off-by: Thierry Laurion <[email protected]>

Add board config for T480

effa9f6

Signed-off-by: Thierry Laurion <[email protected]>

add a new t480.mk dealing with blobs

3a4be96

Signed-off-by: Thierry Laurion <[email protected]>

add dependencies and a script to download and modify essential blobs …

0be89cb

…for t480 Signed-off-by: Thierry Laurion <[email protected]>

change gbe and ifd_16 files

277e4da

Signed-off-by: Thierry Laurion <[email protected]>

modules/coreboot: t480; do not reuse 24.02.01 coreboot buildtack, sin…

fd3745c

…ce its not sharing the same coreboot buildstack (something 25.X.X, need to check) Signed-off-by: Thierry Laurion <[email protected]>

blobs/t480/download-clean-deguard-me.sh: deguard local call needs pyt…

304f6b9

…hon when used under nix docker Signed-off-by: Thierry Laurion <[email protected]>

boards/t480-maximized/t480-maximized.config: use t480 target that cal…

5ce5705

…ls blobs scripts Signed-off-by: Thierry Laurion <[email protected]>

config/linux-t480.config: use config/linux-librem_common-6.1.8.config…

c44285c

… as base Signed-off-by: Thierry Laurion <[email protected]>

bin/fetch_coreboot_crossgcc_archive.sh: change acpica default PFG_BAS…

bdb09c6

…EURL to use one of libreboot web mirror Signed-off-by: Thierry Laurion <[email protected]>

modules/coreboot: t480; state its based on 24.12, do not reuse corebo…

6176f6c

…ot 24.02 buildstack) Signed-off-by: Thierry Laurion <[email protected]>

tlaurion marked this pull request as draft February 11, 2025 18:46

tlaurion added 4 commits February 11, 2025 13:59

patches/coreboot-t480/85278-post-skylake-pr0.patch: remove xeon bits …

32fc31b

…we are not interested into which are conflicting against coreboot upstream commit 2f1e4e5e8515dd350cc9d68b48d32a5b6b02ae6a Signed-off-by: Thierry Laurion <[email protected]>

config/coreboot-t480.config: add PR0, unify against nv41, save in old…

e62b84b

…config Signed-off-by: Thierry Laurion <[email protected]>

config/coreboot-t480.config: unset CONFIG_DISPLAY_FSP_VERSION_INFO ot…

002d107

…herwise build error Signed-off-by: Thierry Laurion <[email protected]>

tlaurion mentioned this pull request Feb 11, 2025

Port Heads to T480 #1885

Closed

boards/t480-maximized/t480-maximized.config: enable pr0 (impacts only…

e8974da

… after kexec call to final OS. Otherwise, problem with coreboot config) Signed-off-by: Thierry Laurion <[email protected]>

add t480 board

f75ddb8

Signed-off-by: gaspar-ilom <[email protected]>

gaspar-ilom mentioned this pull request Feb 12, 2025

add t480 board #1907

Closed

config/coreboot-t480.config: set CONFIG_FSP_USE_REPO=y otherwise buil…

f9ba787

…d error Signed-off-by: Thierry Laurion <[email protected]>

gaspar-ilom mentioned this pull request Mar 6, 2025

do not break other boards with the coreboot hacks made for the t480 tlaurion/heads#25

Closed

gaspar-ilom approved these changes Mar 8, 2025

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tlaurion closed this Mar 9, 2025

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