I am an Electronics and Telecommunications Engineering senior at VNUHCM - University of Science, focused on applied computer vision, machine learning, network communications and embedded systems. My current portfolio is built around evidence-backed repositories rather than broad claims: source code, reports, release assets, visual flows and bounded prototype notes.
My strongest work is in Vietnamese automatic license plate recognition with YOLO/PyTorch and OCR/FastALPR, Python desktop tooling, MATLAB communications simulations, TCP/IP and BLE data paths, FPGA/SoC integration on the Intel DE10-Standard, and STM32 or Silicon Labs embedded workflows. I keep embedded and FPGA work visible because it supports system-level reasoning around AI, communications and hardware-adjacent software.
I am open to internships and junior engineering opportunities in computer vision, machine learning, network/telecommunications engineering, embedded computer vision, firmware, FPGA/SoC systems and platform validation.
| Item | Current value |
|---|---|
| Profile focus | Computer vision, AI/ML, network communications, FPGA/SoC and embedded systems |
| Hiring status | Open to engineering internships and junior engineering opportunities |
| Public repository status | 22 public repositories total, including 19 owned evidence repositories and 3 public forks |
| Review language | US English across profile text, tables, captions, labels and release notes |
| Visual policy | Self-hosted SVG/GIF assets with ASCII-safe SVG text and no line paths behind labels |
| Channel | Link |
|---|---|
| Work email | luonghailong.work@gmail.com |
| Student email | 22207056@student.hcmus.edu.vn |
| Phone | +84 988 114 708 |
| Resume | Luong Hai Long CV |
| GitHub | github.com/lhlizdabezt |
| linkedin.com/in/lhlizdabezt | |
| facebook.com/wageseadrake | |
| instagram.com/lhlizdabezt | |
| YouTube | youtube.com/@lhlizdabezt |
| TikTok | tiktok.com/@wageseadrake |
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Computer vision project using YOLO/PyTorch detection, OCR/FastALPR recognition, Kaggle/IPYNB training evidence, Python desktop inference and LAN demo scope.
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Embedded Linux and FPGA/SoC project where PC or Android clients send TCP payloads to the Cyclone V HPS and then to FPGA-driven seven-segment displays.
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Computer interfacing lab connecting a Silicon Labs BLE SoC, AHT20 sensor data, I2C, UART/VCOM, SQLite logging and BLE RSSI indoor-positioning evidence.
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Roundabout traffic-light controller using sequential digital logic, a mod-12 counter, JK flip-flops, Falstad/CircuitJS simulation and Node.js logic checks.
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Telecommunications coursework covering AWGN, matched filters, BER simulation, BASK/BPSK/BFSK/QPSK, companding and LDPC decoding with report-backed evidence.
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MATLAB practice repository with 23 scripts, lecture and exam PDFs, fading-channel BER, OFDM, MIMO SVD, equalizers and diversity review evidence.
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